From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Sep 2022 14:29:42 +0000 (+0100)
Subject: demo that "setvl." is not reconstructed with Rc=1 mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ee6f45659de4b17b95f72f3ef482d5ed9cf8579;p=openpower-isa.git

demo that "setvl." is not reconstructed with Rc=1 mode
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 506edbca..2096e458 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -20,7 +20,7 @@ class SVSTATETestCase(unittest.TestCase):
             print ("insns", insns)
             for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
                 name = expected[i].split(" ")[0]
-                with self.subTest(name):
+                with self.subTest("%d:%s" % (i, name)):
                     print("instruction", repr(line), repr(expected[i]))
                     self.assertEqual(expected[i], line,
                                      "instruction does not match "
@@ -63,6 +63,13 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_5_sv_management(self):
+        expected = [
+                    "setvl 5,4,5,0,1,1",
+                    "setvl. 5,4,5,0,1,1",
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()