From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Oct 2018 17:05:04 +0000 (+0100)
Subject: add WRITE_FRD macro redirect
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5eec18316782bdf7bbbaee454dfe63ed9538b0ca;p=riscv-isa-sim.git

add WRITE_FRD macro redirect
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 4c1c161..46d0887 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -114,7 +114,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   bool zeroingtarg = false;
 #endif
   sv_insn_t insn(p, sv_enabled, bits, floatintmap, PRED_ARGS, OFFS_ARGS);
-  p->s.set_insn(&insn);
+  p->s.set_insn(&insn, xlen);
 #ifdef USING_NOREGS
   #include INCLUDEFILE
 #else
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 05c55d1..0d8f899 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -1,6 +1,11 @@
 #include "sv_insn_redirect.h"
 #include "processor.h"
 
+void (sv_proc_t::WRITE_FRD)(freg_t value)
+{
+    WRITE_FREG( insn->rd(), value );
+}
+
 void (sv_proc_t::WRITE_RD)(reg_t value)
 {
     WRITE_REG( insn->rd(), value );
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 95550ba..663164d 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -34,15 +34,18 @@ class RS2 {
 class sv_proc_t
 {
 public:
-    sv_proc_t(processor_t *_p) : p(_p), insn(NULL) {}
+    sv_proc_t(processor_t *_p) : p(_p), insn(NULL), xlen(0) {}
     void (WRITE_RD)(reg_t value);
+    void (WRITE_FRD)(freg_t value);
     //reg_t (READ_REG)(uint64_t i);
 
     processor_t *p;
     sv_insn_t *insn;
+    int xlen;
 
-    void set_insn(sv_insn_t *i) {
+    void set_insn(sv_insn_t *i, int x) {
         this->insn = i;
+        this->xlen = x;
     }
 
     reg_t get_rs1();