From: Luke Kenneth Casson Leighton Date: Fri, 22 Jul 2022 14:33:56 +0000 (+0100) Subject: add SX Aurora to table X-Git-Tag: opf_rfc_ls005_v1~1135 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5eec366e0be006c2873e604c47a5308a2556e9a6;p=libreriscv.git add SX Aurora to table --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 0ca434916..5734abf42 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -1,13 +1,14 @@ # ISA Comparison Table -| ISA
name | Num
opcodes | Taxonomy /
Class | Predicate
Masks | Twin
Predication | Explicit
Vector regs | 128-bit | Bigint
capability | LDST
Fault-First | Data-dependent
Fail-first | Predicate-
Result | -|--------------|-------------------|-----------------------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------| -| SVP64 | 5 {1} | Scalable {2} | yes | yes {3} | no {4} | n/a {5} | yes {6} | yes {7} | yes {8} | yes {9} | -| VSX | 700+ | Packed SIMD | no | no | yes {10} | yes | no | no | no | no | -| NEON | ~250 {11} | Predicated SIMD | yes | no | yes | yes | no | no | no | no | -| SVE2 | ~1000 {12} | Scalable HW {13} | yes | no | yes | yes | no | yes {7} | no | no | -| AVX-512 {14} | ~1000s {15} | Predicated SIMD | yes | no | yes | yes | no | no | no | no | -| RVV {16} | ~190 | Scalable {17} | yes | no | yes | yes {18}| no | yes | no | no | +| ISA
name | Num
opcodes | Taxonomy /
Class | Predicate
Masks | Twin
Predication | Explicit
Vector regs | 128-bit | Bigint
capability | LDST
Fault-First | Data-dependent
Fail-first | Predicate-
Result | +|----------------|-------------------|-----------------------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------| +| SVP64 | 5 {1} | Scalable {2} | yes | yes {3} | no {4} | see {5} | yes {6} | yes {7} | yes {8} | yes {9} | +| VSX | 700+ | Packed SIMD | no | no | yes {10} | yes | no | no | no | no | +| NEON | ~250 {11} | Predicated SIMD | yes | no | yes | yes | no | no | no | no | +| SVE2 | ~1000 {12} | Scalable HW {13} | yes | no | yes | yes | no | yes {7} | no | no | +| AVX-512 {14} | ~1000s {15} | Predicated SIMD | yes | no | yes | yes | no | no | no | no | +| RVV {16} | ~190 | Scalable {17} | yes | no | yes | yes {18}| no | yes | no | no | +| Aurora SX {19} | ~250 | Scalable {20} | yes | no | yes | no | no | no | no | no | * {1}: plus EXT001 24-bit prefixing. See [[sv/svp64]] * {2}: A 2-Dimensional Scalable Vector ISA with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]] @@ -18,7 +19,7 @@ * {7} See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf) * {8} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]] * {9} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]] -* {10} VSX's Vector Registers are mis-named: they are PackedSIMD. +* {10} VSX's Vector Registers are mis-named: they are 100% PackedSIMD. AVX-512 is not a Vector ISA either. See [Flynn's Taxonomy](https://en.wikipedia.org/wiki/Flynn%27s_taxonomy) * {11} difficult to ascertain, see [NEON/VFP](https://developer.arm.com/documentation/den0018/a/NEON-and-VFP-Instruction-Summary/List-of-all-NEON-and-VFP-instructions). Critically depends on ARM Scalar instructions * {12} difficult to exactly ascertain, see ARM Architecture Reference Manual Supplement, DDI 0584. Critically depends on ARM Scalar instructions. @@ -29,3 +30,5 @@ * {16}: [RVV Spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc) * {17}: Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction). * {18}: like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements. +* {19}: [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors +* {20}: Like the original Cray Vectors the ISA is independent of the underlying hardware.