From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 Apr 2022 13:05:55 +0000 (+0100)
Subject: doh
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ef408dfe10f2a4e6253b67f8eeded5ba07319dd;p=ls2.git

doh
---

diff --git a/src/ls2.py b/src/ls2.py
index 993186f..89d6c06 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -795,7 +795,7 @@ class DDR3SoC(SoC, Elaboratable):
         # and at the moment that's just UART tx/rx.
         ports = []
         ports += [self.uart.tx_o, self.uart.rx_i]
-        for hr in self.hyperramL
+        for hr in self.hyperram:
             ports += list(hr.ports())
         if hasattr(self, "ddrphy"):
             if hasattr(self.ddrphy, "pads"): # real PHY