From: Florent Kermarrec Date: Fri, 28 Dec 2018 14:14:28 +0000 (+0100) Subject: targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok X-Git-Tag: 24jan2021_ls180~1422 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ef4d09caa1fe19b5165ff7d3b39edf6cc3defd5;p=litex.git targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok --- diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index abe3335a..18aadfde 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -159,7 +159,6 @@ class Platform(LatticePlatform): LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs) def do_finalize(self, fragment): - LatticePlatform.do_finalize(self, fragment) try: self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) except ConstraintError: diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index fd29f16d..921d9002 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -13,47 +13,33 @@ from litex.soc.integration.builder import * from litedram.modules import AS4C32M16 from litedram.phy import GENSDRPHY -from litedram.core.controller import ControllerSettings class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # clk / rst clk100 = platform.request("clk100") rst_n = platform.request("rst_n") - platform.add_period_constraint(clk100, 10.0) # pll self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk100, 100e6) - pll.create_clkout(self.cd_sys, 50e6) + pll.create_clkout(self.cd_sys, 50e6, phase=11) + pll.create_clkout(self.cd_sys_ps, 50e6, phase=20) # FIXME: AsyncResetSynchronizer needs FD1S3BX support. #self.specials += AsyncResetSynchronizer(self.cd_sys, rst) self.comb += self.cd_sys.rst.eq(~rst_n) + platform.add_period_constraint(self.cd_sys.clk, 20.0) + platform.add_period_constraint(self.cd_sys_ps.clk, 20.0) - # sys_clk phase shifted (for sdram) - sdram_ps_clk = self.cd_sys.clk - # FIXME: phase shift with luts, needs PLL support. - sdram_ps_luts = 5 - for i in range(sdram_ps_luts): - new_sdram_ps_clk = Signal() - self.specials += Instance("LUT4", - p_INIT=2, - i_A=sdram_ps_clk, - i_B=0, - i_C=0, - i_D=0, - o_Z=new_sdram_ps_clk) - sdram_ps_clk = new_sdram_ps_clk - self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk) - sdram_clock = platform.request("sdram_clock") - self.comb += sdram_clock.eq(sdram_ps_clk) + # sdram clock + self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) class BaseSoC(SoCSDRAM): @@ -62,7 +48,6 @@ class BaseSoC(SoCSDRAM): platform.add_extension(versa_ecp5._ecp5_soc_hat_io) sys_clk_freq = int(50e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - l2_size=32, integrated_rom_size=0x8000, **kwargs) @@ -73,13 +58,10 @@ class BaseSoC(SoCSDRAM): sdram_module = AS4C32M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, - sdram_module.timing_settings, - controller_settings=ControllerSettings( - with_refresh=False)) # FIXME - + sdram_module.timing_settings) def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to the ULX3S") + parser = argparse.ArgumentParser(description="LiteX SoC port to the Versa ECP5") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() @@ -88,6 +70,5 @@ def main(): builder = Builder(soc, **builder_argdict(args)) builder.build() - if __name__ == "__main__": main()