From: lkcl <lkcl@web>
Date: Thu, 20 Apr 2023 15:44:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5efaad6a8c7c2716a0671b2f99c941924575f03f;p=libreriscv.git

---

diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn
index 059315616..5bcc21faf 100644
--- a/openpower/sv/av_opcodes.mdwn
+++ b/openpower/sv/av_opcodes.mdwn
@@ -40,9 +40,88 @@ All other capabilities (saturate in particular) are achieved with [[sv/svp64]] m
 
 # Instructions
 
-## Average-Add
+## Average Add
 
-## Absolute-Difference
+X-Form
 
-## Absolute-Accumulate
+* avgadd  RT,RA,RB (Rc=0)
+* avgadd. RT,RA,RB (Rc=1)
 
+Pseudo-code:
+
+    a <- [0] * (XLEN+1)
+    b <- [0] * (XLEN+1)
+    a[1:XLEN] <- (RA)
+    b[1:XLEN] <- (RB)
+    r <- (a + b + 1)
+    RT <- r[0:XLEN-1]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
+## Absolute Signed Difference
+
+X-Form
+
+* absds  RT,RA,RB (Rc=0)
+* absds. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+    if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
+    else                RT <- ¬(RB) + (RA) + 1
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
+## Absolute Unsigned Difference
+
+X-Form
+
+* absdu  RT,RA,RB (Rc=0)
+* absdu. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+    if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
+    else                RT <- ¬(RB) + (RA) + 1
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
+## Absolute Accumulate Unsigned Difference
+
+X-Form
+
+* absdacu  RT,RA,RB (Rc=0)
+* absdacu. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+    if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
+    else                 r <- ¬(RB) + (RA) + 1
+    RT <- (RT) + r
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
+## Absolute Accumulate Signed Difference
+
+X-Form
+
+* absdacs  RT,RA,RB (Rc=0)
+* absdacs. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+    if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
+    else                r <- ¬(RB) + (RA) + 1
+    RT <- (RT) + r
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)