From: lkcl <lkcl@web>
Date: Tue, 23 Feb 2021 17:36:14 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~128
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5effaff0d368bca56dbca7d0a66ed0474ea410b0;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index f39639cd9..eea188067 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -124,6 +124,11 @@ SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved int
 
 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
 
+* ISACaller: TODO
+* power-gem5: TODO
+* TestIssuer: TODO
+* Microwatt: TODO
+
 ## VL for-loop
 
 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.