From: Luke Kenneth Casson Leighton Date: Tue, 27 Mar 2018 06:41:15 +0000 (+0100) Subject: begin generating spec files consistently: codes a bit of a mess X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f2ad577a690335adc2915dbacb647471841893f;p=pinmux.git begin generating spec files consistently: codes a bit of a mess --- diff --git a/src/spec/gen.py b/src/spec/gen.py index bba6e44..74abac9 100644 --- a/src/spec/gen.py +++ b/src/spec/gen.py @@ -1,5 +1,6 @@ import os import os.path +from spec.interfaces import Pinouts def specgen(pth, pinouts, bankspec, fixedpins): """ generates a specification of pinouts (tsv files) @@ -13,4 +14,18 @@ def specgen(pth, pinouts, bankspec, fixedpins): os.makedirs(pth) with open(os.path.join(pth, 'interfaces.txt'), 'w') as f: for k in pinouts.fnspec.keys(): - f.write("%s\t%d\n" % (k.lower(), len(pinouts.fnspec[k]))) + s = pinouts.fnspec[k] + f.write("%s\t%d\n" % (k.lower(), len(s))) + s0 = s[s.keys()[0]] # hack, take first + with open(os.path.join(pth, '%s.txt' % k.lower()), 'w') as g: + if len(s0.pingroup) == 1: # only one function, grouped higher up + for ks in s.keys(): # grouped by interface + k = "%s_%s" % (s[ks].fname, s[ks].suffix) + k_ = k.lower() + g.write("%s\t%s\n" % (k_, fntype)) + else: + for pinname in s0.pingroup: + fntype = 'inout' + k_ = k.lower() + pn = pinname.lower() + g.write("%s_%s\t%s\n" % (k_, pn, fntype)) diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py index 1f0cdf6..4e843fe 100644 --- a/src/spec/interfaces.py +++ b/src/spec/interfaces.py @@ -47,11 +47,14 @@ class Pins(object): self.bank = bank self.mux = mux + pingroup = namesuffix(fname, suffix, pingroup) + suffix = '' + res = {} names = {} idx = 0 for name in pingroup[:limit]: - if suffix: + if suffix and name: name_ = "%s_%s" % (name, suffix) else: name_ = name @@ -65,7 +68,7 @@ class Pins(object): res[idx_] = pin names[name] = idx_ for name in pingroup: - if suffix: + if suffix and name: name_ = "%s_%s" % (name, suffix) else: name_ = name @@ -75,7 +78,6 @@ class Pins(object): continue idx_, mux_, bank_ = spec[name] idx_ = names[idx_] - #idx_ += bankspec[bank_] pin = {mux_: (name_, bank_)} if res.has_key(idx_): res[idx_].update(pin) @@ -86,16 +88,16 @@ class Pins(object): def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None): - i2spins = ['IISMCK', 'IISBCK', 'IISLRCK', 'IISDI'] + i2spins = ['MCK', 'BCK', 'LRCK', 'DI'] for i in range(4): - i2spins.append("IISDO%d" % i) + i2spins.append("DO%d" % i) return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) def emmc(bankspec, suffix, offs, bank, mux=1, spec=None): - emmcpins = ['MMCCMD', 'MMCCLK'] + emmcpins = ['CMD', 'CLK'] for i in range(8): - emmcpins.append("MMCD%d" % i) + emmcpins.append("D%d" % i) return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) @@ -105,60 +107,59 @@ def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None, for i in range(4): sdmmcpins.append("D%d" % i) sdmmcpins = sdmmcpins[start:limit] - sdmmcpins = namesuffix('SD', suffix, sdmmcpins) - return Pins('SD', sdmmcpins, bankspec, '', offs, bank, mux, spec, + return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def spi(bankspec, suffix, offs, bank, mux=1, spec=None): - spipins = namesuffix('SPI', suffix, - ['CLK', 'NSS', 'MOSI', 'MISO', 'NSS']) - return Pins('SPI', spipins, bankspec, '', offs, bank, mux, spec, + spipins = ['CLK', 'NSS', 'MOSI', 'MISO', 'NSS'] + return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None): - spipins = namesuffix('QSPI', suffix, - ['CK', 'NSS', 'IO0', 'IO1', 'IO2', 'IO3']) - return Pins('QSPI', spipins, bankspec, '', offs, bank, mux, spec, limit, + spipins = ['CK', 'NSS', 'IO0', 'IO1', 'IO2', 'IO3'] + return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) def i2c(bankspec, suffix, offs, bank, mux=1, spec=None): - spipins = namesuffix('TWI', suffix, - ['SDA', 'SCL']) - return Pins('TWI', spipins, bankspec, '', offs, bank, mux, spec, + spipins = ['SDA', 'SCL'] + return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def jtag(bankspec, suffix, offs, bank, mux=1, spec=None): - uartpins = namesuffix('JTAG', suffix, ['MS', 'DI', 'DO', 'CK']) - return Pins('JTAG', uartpins, bankspec, '', offs, bank, mux, spec, + uartpins = ['MS', 'DI', 'DO', 'CK'] + return Pins('JTAG', uartpins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def uart(bankspec, suffix, offs, bank, mux=1, spec=None): - uartpins = namesuffix('UART', suffix, ['TX', 'RX']) - return Pins('UART', uartpins, bankspec, '', offs, bank, mux, spec, + uartpins = ['TX', 'RX'] + return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def namesuffix(name, suffix, namelist): names = [] for n in namelist: - names.append("%s%s_%s" % (name, suffix, n)) + if n: + names.append("%s%s_%s" % (name, suffix, n)) + else: + names.append("%s_%s" % (name, suffix)) return names def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None): - ulpipins = namesuffix('ULPI', suffix, ['CK', 'DIR', 'STP', 'NXT']) + ulpipins = ['CK', 'DIR', 'STP', 'NXT'] for i in range(8): - ulpipins.append('ULPI%s_D%d' % (suffix, i)) - return Pins('ULPI', ulpipins, bankspec, "", offs, bank, mux, spec, + ulpipins.append('D%d' % i) + return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None): - uartpins = namesuffix('UART', suffix, ['TX', 'RX', 'CTS', 'RTS']) - return Pins('UART', uartpins, bankspec, '', offs, bank, mux, spec, + uartpins = ['TX', 'RX', 'CTS', 'RTS'] + return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None): - ttlpins = ['LCDCK', 'LCDDE', 'LCDHS', 'LCDVS'] + ttlpins = ['CK', 'DE', 'HS', 'VS'] for i in range(24): - ttlpins.append("LCD%d" % i) + ttlpins.append("D%d" % i) return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) @@ -172,8 +173,7 @@ def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None): 'EMDC', 'EMDIO', 'ETXEN', 'ETXCK', 'ECRS', 'ECOL', 'ETXERR'] - buspins = namesuffix('RG', suffix, buspins) - return Pins('RG', buspins, bankspec, '', offs, bank, mux, spec, + return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None): @@ -189,16 +189,14 @@ def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None): buspins.append("BWE%d" % i) for i in range(2,6): buspins.append("CS%d" % i) - buspins = namesuffix('FB', suffix, buspins) - return Pins('FB', buspins, bankspec, "", offs, bank, mux, spec, limit, + return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None): buspins = [] for i in range(8,32): buspins.append("AD%d" % i) - buspins = namesuffix('FB', suffix, buspins) - return Pins('FB', buspins, bankspec, '', offs, bank, mux, spec, limit, + return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None): @@ -248,19 +246,19 @@ def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None): gpiopins = [] for i in range(gpiooffs, gpiooffs+gpionum): - gpiopins.append("%s%s%d" % (prefix, bank, i)) + gpiopins.append("%s%d" % (bank, i)) return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None): gpiopins = [] for i in range(gpiooffs, gpiooffs+gpionum): - gpiopins.append("EINT%d" % (i)) + gpiopins.append("%d" % (i)) return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def pwm(bankspec, suffix, offs, bank, mux=1, spec=None): - return Pins('PWM', ['PWM', ], bankspec, suffix, offs, bank, mux, spec, + return Pins('PWM', ['', ], bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None): @@ -319,6 +317,7 @@ def display_fns(bankspec, pins, function_names): if not pdata.has_key(mux): continue name, bank = pdata[mux] + assert name != None, str(bank) if not fns.has_key(name): fns[name] = [] fns[name].append((pin-bankspec[bank], mux, bank)) @@ -328,7 +327,7 @@ def display_fns(bankspec, pins, function_names): current_fn = None for fname in fnidx: fnbase = find_fn(fname, fn_names) - #print "name", fname + #print "name", fname, fnbase if fnbase != current_fn: if current_fn is not None: print diff --git a/src/spec/m_class.py b/src/spec/m_class.py index be48f12..761703c 100644 --- a/src/spec/m_class.py +++ b/src/spec/m_class.py @@ -241,8 +241,8 @@ def pinspec(): 'TWI1': 'I2C 1', 'TWI2': 'I2C 2', 'TWI3': 'I2C 3', - 'UART0': 'UART (TX/RX/CTS/RTS) 0', - 'UART1': 'UART (TX/RX/CTS/RTS) 1', + 'UARTQ0': 'UART (TX/RX/CTS/RTS) 0', + 'UARTQ1': 'UART (TX/RX/CTS/RTS) 1', 'UART2': 'UART (TX/RX) 2', 'UART3': 'UART (TX/RX) 3', 'UART4': 'UART (TX/RX) 4', @@ -268,7 +268,7 @@ def pinspec(): eoma68 = ['B1:LCD/22', 'ULPI1/8', 'ULPI2', 'MMC', 'SD1', 'UART3', 'TWI3', 'SPI2', 'E2:SD2',] - eoma68_eint = ['EINT16', 'EINT17', 'EINT18', 'EINT19'] + eoma68_eint = ['EINT_16', 'EINT_17', 'EINT_18', 'EINT_19'] eoma68_pwm = ['D1:PWM_2'] descriptions = { 'MMC': 'internal (on Card)', @@ -302,8 +302,8 @@ def pinspec(): 'JTAG1', 'A3:UART2', 'E2:UART1', 'C3:UART0', 'F2:TWI1', 'D2:TWI2', 'D2:TWI3', 'SPI2', 'QSPI', 'F2:SD3'] industrial_pwm = ['F2:PWM_0', 'F2:PWM_1', 'D1:PWM_2'] - industrial_eint = ['EINT24', 'EINT25', 'EINT26', 'EINT27', - 'EINT20', 'EINT21', 'EINT22', 'EINT23'] + industrial_eint = ['EINT_24', 'EINT_25', 'EINT_26', 'EINT_27', + 'EINT_20', 'EINT_21', 'EINT_22', 'EINT_23'] unused_pins = check_functions("Industrial", bankspec, fns, pinouts, industrial, industrial_eint, industrial_pwm) @@ -322,8 +322,8 @@ def pinspec(): 'A3:UART2', 'E2:UART1', 'C3:UART0', 'B2:UART4', 'B2:UART3', 'F2:TWI1', 'D2:TWI2', 'D2:TWI3', 'SPI2', 'QSPI', 'F2:SD3'] industrial_pwm = ['F2:PWM_0', 'F2:PWM_1', 'D1:PWM_2'] - industrial_eint = ['EINT24', 'EINT25', 'EINT26', 'EINT27', - 'EINT20', 'EINT21', 'EINT22', 'EINT23'] + industrial_eint = ['EINT_24', 'EINT_25', 'EINT_26', 'EINT_27', + 'EINT_20', 'EINT_21', 'EINT_22', 'EINT_23'] ind_descriptions = { 'B2:SPI1': 'Used for 320x240 or 640x480 etc. SPI-based LCD.\n' 'Frees up large numbers of GPIO from RGB/TTL bank' @@ -347,18 +347,18 @@ def pinspec(): 'D3:TWI1', 'D2:TWI3', 'SPI2', 'QSPI'] tablet_pwm = ['F2:PWM_0', # LCD_BACKLIGHT 'F2:PWM_1', 'D1:PWM_2'] - tablet_eint = ['EINT24', # BT_HOST_WAKE - 'EINT25', # WIFI_HOST_WAKE - 'EINT26', # CTP_INT - 'EINT27', # GSENSOR_INT - 'EINT8', # GPS_INT - 'EINT7', # TILT_SENSOR_INT - 'EINT22', # COMPASS_INT - 'EINT23', # MCU_INT - 'EINT16', # PMIC_INT - 'EINT17', # PWR_BUTTON_INT - 'EINT30', # OTG_ID - 'EINT31', + tablet_eint = ['EINT_24', # BT_HOST_WAKE + 'EINT_25', # WIFI_HOST_WAKE + 'EINT_26', # CTP_INT + 'EINT_27', # GSENSOR_INT + 'EINT_8', # GPS_INT + 'EINT_7', # TILT_SENSOR_INT + 'EINT_22', # COMPASS_INT + 'EINT_23', # MCU_INT + 'EINT_16', # PMIC_INT + 'EINT_17', # PWR_BUTTON_INT + 'EINT_30', # OTG_ID + 'EINT_31', ] descriptions = { 'B1:LCD/22': @@ -396,18 +396,18 @@ def pinspec(): 'F2:PWM_0': 'LCD Backlight', 'F2:PWM_1': 'Spare? PWM (or extra GPIO / EINT)', 'D1:PWM_2': 'Spare? PWM (or extra GPIO / EINT)', - 'EINT24': 'BT_HOST_WAKE', - 'EINT25': 'WIFI_HOST_WAKE', - 'EINT26': 'CTP_INT', - 'EINT27': 'GSENSOR_INT', - 'EINT8': 'GPS_INT', - 'EINT7': 'TILT_SENSOR_INT', - 'EINT22': 'COMPASS_INT', - 'EINT23': 'MCU_INT', - 'EINT16': 'PMIC_INT', - 'EINT17': 'PWR_BUTTON_INT', - 'EINT30': 'OTG_ID', - 'EINT31': 'Spare?', + 'EINT_24': 'BT_HOST_WAKE', + 'EINT_25': 'WIFI_HOST_WAKE', + 'EINT_26': 'CTP_INT', + 'EINT_27': 'GSENSOR_INT', + 'EINT_8': 'GPS_INT', + 'EINT_7': 'TILT_SENSOR_INT', + 'EINT_22': 'COMPASS_INT', + 'EINT_23': 'MCU_INT', + 'EINT_16': 'PMIC_INT', + 'EINT_17': 'PWR_BUTTON_INT', + 'EINT_30': 'OTG_ID', + 'EINT_31': 'Spare?', } unused_pins = check_functions("Smartphone / Tablet", bankspec, fns, pinouts, @@ -425,10 +425,10 @@ def pinspec(): 'D2:TWI3', 'QSPI'] laptop_pwm = ['F2:PWM_0', # LCD_BACKLIGHT ] - laptop_eint = ['EINT20', # BT_HOST_WAKE - 'EINT21', # WIFI_HOST_WAKE - 'EINT9', # MCU_INT - 'EINT31', # PMIC_INT + laptop_eint = ['EINT_20', # BT_HOST_WAKE + 'EINT_21', # WIFI_HOST_WAKE + 'EINT_9', # MCU_INT + 'EINT_31', # PMIC_INT ] descriptions = { 'D1:FB/17': 'FlexBus. Connect to DM9000 or AX99896A MCU-style Bus\n' @@ -460,10 +460,10 @@ def pinspec(): 'MCU EINT-capable GPIO may be used to generate extra EINTs\n' 'on the single MCU_INT line, if really needed', 'F2:PWM_0': 'LCD Backlight', - 'EINT20': 'BT_HOST_WAKE', - 'EINT21': 'WIFI_HOST_WAKE', - 'EINT9': 'MCU_INT', - 'EINT31': 'PMIC_INT', + 'EINT_20': 'BT_HOST_WAKE', + 'EINT_21': 'WIFI_HOST_WAKE', + 'EINT_9': 'MCU_INT', + 'EINT_31': 'PMIC_INT', } unused_pins = check_functions("Laptop / Netbook", bankspec, fns, pinouts, @@ -484,21 +484,21 @@ def pinspec(): 'D2:TWI3', 'QSPI'] iot_pwm = ['F2:PWM_0', # LCD_BACKLIGHT ] - iot_eint = [ 'EINT5', # 'HSPA_MST_RDY', - 'EINT6', # 'HSPA_SL_RDY', - 'EINT7', # 'HSPA_RING', - 'EINT8', # 'WL_PMU_EN', - 'EINT9', # HSPA_GPIO1 - 'EINT10', # IR_DT - 'EINT11', # 'BT_PCM_CLK', - 'EINT12', # 'BT_PCM_DIN', - 'EINT13', # 'BT_PCM_SYNC', - 'EINT14', # 'BT_PCM_DOUT', - 'EINT16', # 'USB_DRVVBUS', - 'EINT17', # 'USB_VBUSDET', - 'EINT21', # 'USB_ID', - 'EINT30', # 'CTP_INT', - 'EINT31', # 'SD_DET#', + iot_eint = [ 'EINT_5', # 'HSPA_MST_RDY', + 'EINT_6', # 'HSPA_SL_RDY', + 'EINT_7', # 'HSPA_RING', + 'EINT_8', # 'WL_PMU_EN', + 'EINT_9', # HSPA_GPIO1 + 'EINT_10', # IR_DT + 'EINT_11', # 'BT_PCM_CLK', + 'EINT_12', # 'BT_PCM_DIN', + 'EINT_13', # 'BT_PCM_SYNC', + 'EINT_14', # 'BT_PCM_DOUT', + 'EINT_16', # 'USB_DRVVBUS', + 'EINT_17', # 'USB_VBUSDET', + 'EINT_21', # 'USB_ID', + 'EINT_30', # 'CTP_INT', + 'EINT_31', # 'SD_DET#', ] descriptions = { 'B1:LCD': @@ -541,7 +541,7 @@ def pinspec(): 'GPIOD18': 'LCD_RS', 'GPIOD21': 'LCD_CSN', - 'EINT5': 'HSPA_MST_RDY', + 'EINT_5': 'HSPA_MST_RDY', 'EINT6': 'HSPA_SL_RDY', 'EINT7': 'HSPA_RING', 'EINT8': 'WL_PMU_EN',