From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 24 Jul 2020 15:12:32 +0000 (+0100)
Subject: got fed up with bit-slice ordering crap.  cut it out
X-Git-Tag: semi_working_ecp5~562
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f42acd0348e127eb1a2edf5aae224687b5c5917;p=soc.git

got fed up with bit-slice ordering crap.  cut it out
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 43bc2c24..72bdaf4d 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -19,7 +19,7 @@ from soc.decoder.power_enums import MicrOp
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
-from soc.consts import MSR, MSRb, PI, TT, field, field_slice
+from soc.consts import MSR, PI, TT, field, field_slice
 
 
 def msr_copy(msr_o, msr_i, zero_me=True):
@@ -103,11 +103,8 @@ class TrapMainStage(PipeModBase):
         comb += msr_o.data[MSR.VEC].eq(0)
         comb += msr_o.data[MSR.FP].eq(0)
         comb += msr_o.data[MSR.PMM].eq(0)
-        # XXX no.  slice quantity still inverted producing an empty list
-        # https://bugs.libre-soc.org/show_bug.cgi?id=325#c120
-        # also add a comment explaining this very non-obvious
-        # behaviour.
-        comb += field(msr_o.data, MSRb.TEs, MSRb.TEe).eq(0)
+        comb += msr_o.data[MSR.TEs].eq(0) # this is only 2 bits
+        comb += msr_o.data[MSR.TEe].eq(0) # so just zero them both
         comb += msr_o.data[MSR.UND].eq(0)
         if msr_hv is not None:
             comb += msr_o.data[MSR.HV].eq(msr_hv)