From: Gabe Black <gabe.black@gmail.com>
Date: Thu, 21 Jan 2021 11:43:35 +0000 (-0800)
Subject: arch-sparc: Stop "using namespace std"
X-Git-Tag: develop-gem5-snapshot~241
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f6f6d0850b10d4d86b99b2ece92464dd85fc1c1;p=gem5.git

arch-sparc: Stop "using namespace std"

Change-Id: I4a1019b5978b08b4999edfe5f65ef7eae06481c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39560
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index b48055800..a80e64907 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -42,8 +42,6 @@
 #include "sim/full_system.hh"
 #include "sim/process.hh"
 
-using namespace std;
-
 namespace SparcISA
 {
 
@@ -340,7 +338,7 @@ doREDFault(ThreadContext *tc, TrapType tt)
     tc->setMiscRegNoEffect(MISCREG_TT, tt);
 
     // Update GL
-    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
+    tc->setMiscReg(MISCREG_GL, std::min<int>(GL+1, MaxGL));
 
     bool priv = pstate.priv; // just save the priv bit
     pstate = 0;
@@ -424,9 +422,9 @@ doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
 
     // Update the global register level
     if (!gotoHpriv)
-        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
+        tc->setMiscReg(MISCREG_GL, std::min<int>(GL + 1, MaxPGL));
     else
-        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
+        tc->setMiscReg(MISCREG_GL, std::min<int>(GL + 1, MaxGL));
 
     // pstate.mm is unchanged
     pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index da814e3e3..1cef0fc9b 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -86,6 +86,5 @@ output exec {{
 #include "sim/sim_exit.hh"
 
 using namespace SparcISA;
-using namespace std;
 }};
 
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index b292c86a8..0923eeb46 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -45,7 +45,6 @@
 #include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
-using namespace std;
 using namespace SparcISA;
 
 SparcProcess::SparcProcess(const ProcessParams &params,
@@ -142,7 +141,7 @@ SparcProcess::argsInit(int pageSize)
 
     std::vector<AuxVector<IntType>> auxv;
 
-    string filename;
+    std::string filename;
     if (argv.size() < 1)
         filename = "";
     else
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index cf91f3d9b..a2988c6f0 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -140,7 +140,6 @@
 #include "sim/process.hh"
 #include "sim/system.hh"
 
-using namespace std;
 using namespace SparcISA;
 
 RemoteGDB::RemoteGDB(System *_system, ThreadContext *c, int _port)
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index b0b9f591f..3f33816bc 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -38,7 +38,6 @@
 #include "sim/system.hh"
 
 using namespace SparcISA;
-using namespace std;
 
 
 void
@@ -66,10 +65,10 @@ ISA::checkSoftInt()
 }
 
 // These functions map register indices to names
-static inline string
+static inline std::string
 getMiscRegName(RegIndex index)
 {
-    static string miscRegName[NumMiscRegs] =
+    static std::string miscRegName[NumMiscRegs] =
         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
          "stick", "stick_cmpr",