From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Apr 2021 16:51:19 +0000 (+0100)
Subject: add SPBlock_512W64B8W.v to sources
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f79875266bb30f210a53d2b181ba55b198cfe0d;p=libresoc-litex.git

add SPBlock_512W64B8W.v to sources
---

diff --git a/Makefile b/Makefile
index a235508..1bfeeb3 100644
--- a/Makefile
+++ b/Makefile
@@ -4,6 +4,7 @@ ls1804k:
 	cp build/ls180sram4k/gateware/mem.init .
 	cp build/ls180sram4k/gateware/mem_1.init .
 	cp libresoc/libresoc.v .
+	cp libresoc/SPBlock_512W64B8W.v .
 	yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'
 	yosys -p 'read_verilog ls180.v' \
@@ -19,6 +20,7 @@ ls180:
 	cp build/ls180/gateware/mem.init .
 	cp build/ls180/gateware/mem_1.init .
 	cp libresoc/libresoc.v .
+	cp libresoc/SPBlock_512W64B8W.v .
 	yosys -p 'read_verilog libresoc.v' \
 	      -p 'read_verilog ls180.v' \
 	      -p 'proc' \
diff --git a/SPBlock_512W64B8W.v b/SPBlock_512W64B8W.v
deleted file mode 100644
index ddab968..0000000
--- a/SPBlock_512W64B8W.v
+++ /dev/null
@@ -1,7 +0,0 @@
-(* blackbox = 1 *)
-module SPBlock_512W64B8W(input [8:0] a,
-			 input [63:0] d,
-			 output [63:0] q,
-			 input [7:0] we,
-			 input clk);
-endmodule // SPBlock_512W64B8W
diff --git a/libresoc/SPBlock_512W64B8W.v b/libresoc/SPBlock_512W64B8W.v
new file mode 100644
index 0000000..ddab968
--- /dev/null
+++ b/libresoc/SPBlock_512W64B8W.v
@@ -0,0 +1,7 @@
+(* blackbox = 1 *)
+module SPBlock_512W64B8W(input [8:0] a,
+			 input [63:0] d,
+			 output [63:0] q,
+			 input [7:0] we,
+			 input clk);
+endmodule // SPBlock_512W64B8W
diff --git a/libresoc/core.py b/libresoc/core.py
index 66f3eb2..0146511 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -368,6 +368,7 @@ class LibreSoC(CPU):
     def add_sources(platform):
         cdir = os.path.dirname(__file__)
         platform.add_source(os.path.join(cdir, "libresoc.v"))
+        platform.add_source(os.path.join(cdir, "SPBlock_512W64B8W.v"))
 
     def do_finalize(self):
         self.specials += Instance("test_issuer", **self.cpu_params)