From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Sep 2019 22:59:10 +0000 (-0700)
Subject: Tidy up
X-Git-Tag: working-ls180~1039^2~166
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f8f0e13833ef052adb4d2d3deb8e965734127fd;p=yosys.git

Tidy up
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index e611bfb3b..afbd6ef81 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -390,11 +390,6 @@ endcode
 subpattern in_dffe
 arg dffQ clock dffenpol_
 
-code
-	dff = nullptr;
-	dffmux = nullptr;
-endcode
-
 match ff
 	select ff->type.in($dff)
 	// DSP48E1 does not support clock inversion
@@ -428,8 +423,10 @@ code dffQ
 		if (!(nusers(dffQ) >= 3 && nusers(dffD) == 2))
 			dffQ = SigSpec();
 	}
-	else
+	else {
+		dff = nullptr;
 		dffQ = SigSpec();
+	}
 endcode
 
 match ffmux
@@ -454,4 +451,6 @@ code
 		dffenpol = dffenpol_;
 		dffD = port(ffmux, dffenpol ? \B : \A);
 	}
+	else
+		dffmux = nullptr;
 endcode