From: lkcl <lkcl@web>
Date: Wed, 30 Dec 2020 15:51:04 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~720
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f930469aac0a382639ef25c662a91a95b9a1862;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 409966721..2c3d085b0 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -165,13 +165,14 @@ The following fields are common to all Remapped Encodings:
 | SUBVL         | `6:7`      | Sub-vector length                   |                          
 | MODE          | `19:23`    | changes Vector behaviour               |
 
-Bits 9 to 18 are further decoded depending on RM category for the instruction.
-
 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
 * ELWIDTH overrides the instruction's operand width
 * MASK and MASK_KIND provide predication (two types of sources: scalar INT and Vector CR).
 
+Bits 9 to 18 are further decoded depending on RM category for the instruction.
+These are given designations such as `RM-1P-3S1D` which indicate that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
+
 # Mode
 
 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).