From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Wed, 27 Sep 2023 07:32:27 +0000 (+0100)
Subject: Added english language description and brackets for lwbrx instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f9974443f5de178469221c8122e7b7cef39dd9f;p=openpower-isa.git

Added english language description and brackets for lwbrx instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 15774d3c..337e7c53 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -686,6 +686,17 @@ Pseudo-code:
     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
                     || load_data[8:15]  || load_data[0:7])
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). Bits 0:7 of the word in storage addressed
+    by EA are loaded into RT[56:63]. Bits 8:15 of the word in
+    storage addressed by EA are loaded into RT[48:55] . Bits
+    16:23 of the word in storage addressed by EA are
+    loaded into RT[40:47]. Bits 24:31 of the word in storage
+    addressed by EA are loaded into RT 32:39 . RT[0:31] are
+    set to 0.
+
 Special Registers Altered:
 
     None