From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Nov 2013 15:49:58 +0000 (+0100)
Subject: Improved handling of techmap special wires
X-Git-Tag: yosys-0.2.0~325
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5f9c7fc6eadd7bc70e13df4131c059ec9ae18103;p=yosys.git

Improved handling of techmap special wires
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 0bc19c348..e273769d1 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -78,7 +78,7 @@ static TechmapWires techmap_find_special_wires(RTLIL::Module *module)
 			record.value = it.second;
 			result[p].push_back(record);
 			it.second->attributes["\\keep"] = RTLIL::Const(1);
-			it.second->attributes["\\_techmap_attr_"] = RTLIL::Const(1);
+			it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
 		}
 	}
 
@@ -112,6 +112,8 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module,
 		w->port_input = false;
 		w->port_output = false;
 		w->port_id = 0;
+		if (it.second->get_bool_attribute("\\_techmap_special_"))
+			w->attributes.clear();
 		module->wires[w->name] = w;
 		design->select(module, w);
 	}