From: yimmanuel3@f4ac60d763911c3fa518755176e4b9ed455c75d8 Date: Sun, 2 Feb 2020 08:56:47 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~3621 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5fa699e36b2cdee26059a17d4132dd2e72635566;p=libreriscv.git --- diff --git a/index.mdwn b/index.mdwn index bf6c35dfc..04913fb8a 100644 --- a/index.mdwn +++ b/index.mdwn @@ -14,6 +14,18 @@ LibreSOC strives to deliver a fully capable and competitive Libre integrated Sys Right now, we're targeting an (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC. +## But Why do I need a LibreSOC? +Its entirely possible that you're OK with the fact that modern processors have +[backdoors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html) that the bad actors +regularly exploit. + +But beyond the contemporary ever increasing cry for privacy, is a very real need for reliable safety critical processors. +LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access +to that processor's source and a cycle accurate HDL simulator that guarantees developer's their code behaves as they +expect. An ISA level simulator is no longer satisfactory. + +Refer to this [paper](https://ieeexplore.ieee.org/document/4519604) authored by Cyberphysical System expert Ed-Lee for more details. + ## Still Got Questions? Read about the business and practical benefits of a LibreSOC below.