From: lkcl <lkcl@web>
Date: Thu, 16 Sep 2021 16:52:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5faeae43d7f4e2b4d91e49baef05f4522dacb01a;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index d288e8115..e33cb923c 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -71,9 +71,9 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
 | - | - | ----- | --- |---------|----------------- |
 |sz |SNZ| 00    |   0 |  dz  /  | normal mode                      |
-| / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-| / | / | 00    |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
-| / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
+|sz |SNZ| 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
+|sz |SNZ| 00    |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
+|sz |SNZ| 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
 |sz |SNZ| 01/10 | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 01/10 | inv |  dz /   | Ffirst 5-bit mode       |
 |sz |SNZ| 11    | inv | CR-bit  |  3-bit pred-result CR sel |