From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 19:03:51 +0000 (-0700)
Subject: $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
X-Git-Tag: working-ls180~1191^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5fb27c071bb072644dbb38cf8a516628c2afe15b;p=yosys.git

$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
---

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 4b55297dd..c0ea742e2 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 400 379 316
 259 231 126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index b85346370..d73b6d649 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 589 558 465
 675 609 186 
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 95c2c3d81..42d666051 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 1231 1205 874
 675  609  278
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index abba18c37..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -45,7 +45,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
 `ifdef _ABC
-		\$__ICE40_CARRY_LUT4 carry (
+		\$__ICE40_FULL_ADDER carry (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 5dca63e19..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -63,7 +63,7 @@ endmodule
 `endif
 
 `ifdef _ABC
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
     .I1(B),
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index cf36f5cfb..609facc93 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -142,7 +142,7 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 38910dffa..e492454fb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "$__ICE40_CARRY_LUT4")
+		if (cell->type == "$__ICE40_FULL_ADDER")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -114,7 +114,7 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
 				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });