From: R. Ou <rqou@robertou.com>
Date: Mon, 17 Feb 2020 08:54:33 +0000 (-0800)
Subject: extract_counter: Fix clock enable
X-Git-Tag: working-ls180~785^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5fc180ed2d6da82892c7499392c0c5057c3aeec8;p=yosys.git

extract_counter: Fix clock enable
---

diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index 69fdaf269..d1a0f6dec 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -509,13 +509,15 @@ void counter_worker(
 		cell->setPort(ID(CE), extract.ce);
 	}
 	else
+	{
 		cell->setParam(ID(HAS_CE), RTLIL::Const(0));
+		cell->setPort(ID(CE), RTLIL::Const(1));
+	}
 
 	//Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
 	cell->setParam(ID(HAS_POUT), RTLIL::Const(0));
 	cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0));
 	cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
-	cell->setPort(ID(CE), RTLIL::Const(1));
 	cell->setPort(ID(UP), RTLIL::Const(0));
 
 	//Hook up any parallel outputs