From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Wed, 4 Aug 2010 03:48:02 +0000 (-0700)
Subject: [pk,sim,xcc] Renamed instructions to RISC-V spec
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ff63bcd7935cad840fd25844dfb590010bd2e12;p=riscv-isa-sim.git

[pk,sim,xcc] Renamed instructions to RISC-V spec

All word-sized arithmetic operations are now postfixed with 'w',
and all double-word-sized arithmetic operations are no longer
prefixed with 'd'.  mtc0/mfc0 are removed and replaced with
mfpcr/mtpcr/mwfpcr/mwtpcr.
---

diff --git a/riscv/execute.h b/riscv/execute.h
index 54bf52d..4715b7f 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -585,7 +585,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        #include "insns/daddi.h"
+        #include "insns/addiw.h"
         break;
       }
       case 0x2:
@@ -714,14 +714,14 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/srlv.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea004020)
+        if((insn.bits & 0xfe007fe0) == 0xea004060)
         {
-          #include "insns/sllv.h"
+          #include "insns/srav.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea004060)
+        if((insn.bits & 0xfe007fe0) == 0xea004020)
         {
-          #include "insns/srav.h"
+          #include "insns/sllv.h"
           break;
         }
         #include "insns/unimp.h"
@@ -766,14 +766,14 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xec000020)
+        if((insn.bits & 0xfe007fe0) == 0xec000000)
         {
-          #include "insns/dsub.h"
+          #include "insns/addw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec000000)
+        if((insn.bits & 0xfe007fe0) == 0xec000020)
         {
-          #include "insns/dadd.h"
+          #include "insns/subw.h"
           break;
         }
         #include "insns/unimp.h"
@@ -782,56 +782,56 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fe0) == 0xec0010e0)
         {
-          #include "insns/dremu.h"
+          #include "insns/remuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec001080)
+        if((insn.bits & 0xfe007fe0) == 0xec0010a0)
         {
-          #include "insns/ddiv.h"
+          #include "insns/divuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec0010c0)
+        if((insn.bits & 0xfe007fe0) == 0xec001060)
         {
-          #include "insns/drem.h"
+          #include "insns/mulhuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec001060)
+        if((insn.bits & 0xfe007fe0) == 0xec001000)
         {
-          #include "insns/dmulhu.h"
+          #include "insns/mulw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec001000)
+        if((insn.bits & 0xfe007fe0) == 0xec0010c0)
         {
-          #include "insns/dmul.h"
+          #include "insns/remw.h"
           break;
         }
         if((insn.bits & 0xfe007fe0) == 0xec001040)
         {
-          #include "insns/dmulh.h"
+          #include "insns/mulhw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec0010a0)
+        if((insn.bits & 0xfe007fe0) == 0xec001080)
         {
-          #include "insns/ddivu.h"
+          #include "insns/divw.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x4:
       {
-        if((insn.bits & 0xfe007fe0) == 0xec004020)
+        if((insn.bits & 0xfe007fe0) == 0xec004060)
         {
-          #include "insns/dsllv.h"
+          #include "insns/sravw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec004060)
+        if((insn.bits & 0xfe007fe0) == 0xec004020)
         {
-          #include "insns/dsrav.h"
+          #include "insns/sllvw.h"
           break;
         }
         if((insn.bits & 0xfe007fe0) == 0xec004040)
         {
-          #include "insns/dsrlv.h"
+          #include "insns/srlvw.h"
           break;
         }
         #include "insns/unimp.h"
@@ -840,26 +840,26 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfff07c00) == 0xec005000)
         {
-          #include "insns/dsll.h"
+          #include "insns/sllw.h"
           break;
         }
         if((insn.bits & 0xfff07c00) == 0xec005400)
         {
-          #include "insns/dsll32.h"
+          #include "insns/sll32.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x6:
       {
-        if((insn.bits & 0xfff07c00) == 0xec006400)
+        if((insn.bits & 0xfff07c00) == 0xec006000)
         {
-          #include "insns/dsrl32.h"
+          #include "insns/srlw.h"
           break;
         }
-        if((insn.bits & 0xfff07c00) == 0xec006000)
+        if((insn.bits & 0xfff07c00) == 0xec006400)
         {
-          #include "insns/dsrl.h"
+          #include "insns/srl32.h"
           break;
         }
         #include "insns/unimp.h"
@@ -868,12 +868,12 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfff07c00) == 0xec007400)
         {
-          #include "insns/dsra32.h"
+          #include "insns/sra32.h"
           break;
         }
         if((insn.bits & 0xfff07c00) == 0xec007000)
         {
-          #include "insns/dsra.h"
+          #include "insns/sraw.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1101,7 +1101,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc004000)
         {
-          #include "insns/mfc0.h"
+          #include "insns/mfpcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1110,7 +1110,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc005000)
         {
-          #include "insns/dmfc0.h"
+          #include "insns/mwfpcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1119,7 +1119,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc006000)
         {
-          #include "insns/mtc0.h"
+          #include "insns/mtpcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1128,7 +1128,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xfe007fff) == 0xfc007000)
         {
-          #include "insns/dmtc0.h"
+          #include "insns/mwtpcr.h"
           break;
         }
         #include "insns/unimp.h"
diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index bfbc485..746cd80 100644
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1,2 @@
-RC = sext32(RA + RB);
-
+require64;
+RC = RA + RB;
diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index 6935cca..b6b208d 100644
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1,2 @@
-RA = sext32(SIMM + RB);
+require64;
+RA = SIMM + RB;
diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
new file mode 100644
index 0000000..6935cca
--- /dev/null
+++ b/riscv/insns/addiw.h
@@ -0,0 +1 @@
+RA = sext32(SIMM + RB);
diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
new file mode 100644
index 0000000..bfbc485
--- /dev/null
+++ b/riscv/insns/addw.h
@@ -0,0 +1,2 @@
+RC = sext32(RA + RB);
+
diff --git a/riscv/insns/dadd.h b/riscv/insns/dadd.h
deleted file mode 100644
index 746cd80..0000000
--- a/riscv/insns/dadd.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RA + RB;
diff --git a/riscv/insns/daddi.h b/riscv/insns/daddi.h
deleted file mode 100644
index b6b208d..0000000
--- a/riscv/insns/daddi.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RA = SIMM + RB;
diff --git a/riscv/insns/ddiv.h b/riscv/insns/ddiv.h
deleted file mode 100644
index f0c2d2b..0000000
--- a/riscv/insns/ddiv.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RA) / sreg_t(RB);
diff --git a/riscv/insns/ddivu.h b/riscv/insns/ddivu.h
deleted file mode 100644
index a4e3f4f..0000000
--- a/riscv/insns/ddivu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RA / RB;
diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index e595c85..f0c2d2b 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA)/int32_t(RB));
-
+require64;
+RC = sreg_t(RA) / sreg_t(RB);
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 68f96a5..a4e3f4f 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA)/uint32_t(RB));
-
+require64;
+RC = RA / RB;
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
new file mode 100644
index 0000000..68f96a5
--- /dev/null
+++ b/riscv/insns/divuw.h
@@ -0,0 +1,2 @@
+RC = sext32(uint32_t(RA)/uint32_t(RB));
+
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
new file mode 100644
index 0000000..e595c85
--- /dev/null
+++ b/riscv/insns/divw.h
@@ -0,0 +1,2 @@
+RC = sext32(int32_t(RA)/int32_t(RB));
+
diff --git a/riscv/insns/dmfc0.h b/riscv/insns/dmfc0.h
deleted file mode 100644
index 7808458..0000000
--- a/riscv/insns/dmfc0.h
+++ /dev/null
@@ -1,29 +0,0 @@
-require_supervisor;
-require64;
-
-switch(insn.rtype.rb)
-{
-  case 0:
-    RA = sr;
-    break;
-  case 1:
-    RA = epc;
-    break;
-  case 2:
-    RA = badvaddr;
-    break;
-  case 3:
-    RA = ebase;
-    break;
-
-  case 8:
-    RA = MEMSIZE >> 12;
-    break;
-
-  case 17:
-    RA = sim->get_fromhost();
-    break;
-
-  default:
-    RA = -1;
-}
diff --git a/riscv/insns/dmtc0.h b/riscv/insns/dmtc0.h
deleted file mode 100644
index 67195a6..0000000
--- a/riscv/insns/dmtc0.h
+++ /dev/null
@@ -1,19 +0,0 @@
-require_supervisor;
-require64;
-
-switch(insn.rtype.rb)
-{
-  case 0:
-    set_sr(RA);
-    break;
-  case 1:
-    epc = RA;
-    break;
-  case 3:
-    ebase = RA & ~0xFFF;
-    break;
-
-  case 16:
-    sim->set_tohost(RA);
-    break;
-}
diff --git a/riscv/insns/dmul.h b/riscv/insns/dmul.h
deleted file mode 100644
index 9c81285..0000000
--- a/riscv/insns/dmul.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RA * RB;
diff --git a/riscv/insns/dmulh.h b/riscv/insns/dmulh.h
deleted file mode 100644
index 2d7ca4c..0000000
--- a/riscv/insns/dmulh.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require64;
-int64_t rb = RA;
-int64_t ra = RB;
-RC = (int128_t(rb) * int128_t(ra)) >> 64;
diff --git a/riscv/insns/dmulhu.h b/riscv/insns/dmulhu.h
deleted file mode 100644
index 45e9704..0000000
--- a/riscv/insns/dmulhu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = (uint128_t(RA) * uint128_t(RB)) >> 64;
diff --git a/riscv/insns/drem.h b/riscv/insns/drem.h
deleted file mode 100644
index dfece43..0000000
--- a/riscv/insns/drem.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RA) % sreg_t(RB);
diff --git a/riscv/insns/dremu.h b/riscv/insns/dremu.h
deleted file mode 100644
index e8ee6b1..0000000
--- a/riscv/insns/dremu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RA % RB;
diff --git a/riscv/insns/dsll.h b/riscv/insns/dsll.h
deleted file mode 100644
index a07e038..0000000
--- a/riscv/insns/dsll.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB << SHAMT;
diff --git a/riscv/insns/dsll32.h b/riscv/insns/dsll32.h
deleted file mode 100644
index cfd9ba3..0000000
--- a/riscv/insns/dsll32.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB << (32+SHAMT);
diff --git a/riscv/insns/dsllv.h b/riscv/insns/dsllv.h
deleted file mode 100644
index 7e81e6b..0000000
--- a/riscv/insns/dsllv.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB << (RA & 0x3F);
diff --git a/riscv/insns/dsra.h b/riscv/insns/dsra.h
deleted file mode 100644
index 19118f0..0000000
--- a/riscv/insns/dsra.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RB) >> SHAMT;
diff --git a/riscv/insns/dsra32.h b/riscv/insns/dsra32.h
deleted file mode 100644
index 001e3bd..0000000
--- a/riscv/insns/dsra32.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = sreg_t(RB) >> (32+SHAMT);
diff --git a/riscv/insns/dsrav.h b/riscv/insns/dsrav.h
deleted file mode 100644
index ec6fee8..0000000
--- a/riscv/insns/dsrav.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB >> (RA & 0x3F);
diff --git a/riscv/insns/dsrl.h b/riscv/insns/dsrl.h
deleted file mode 100644
index 47426b1..0000000
--- a/riscv/insns/dsrl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB >> SHAMT;
diff --git a/riscv/insns/dsrl32.h b/riscv/insns/dsrl32.h
deleted file mode 100644
index 5d52dea..0000000
--- a/riscv/insns/dsrl32.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB >> (32+SHAMT);
diff --git a/riscv/insns/dsrlv.h b/riscv/insns/dsrlv.h
deleted file mode 100644
index ec6fee8..0000000
--- a/riscv/insns/dsrlv.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RB >> (RA & 0x3F);
diff --git a/riscv/insns/dsub.h b/riscv/insns/dsub.h
deleted file mode 100644
index e7ac407..0000000
--- a/riscv/insns/dsub.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require64;
-RC = RA - RB;
diff --git a/riscv/insns/mfc0.h b/riscv/insns/mfc0.h
deleted file mode 100644
index 8a0a84a..0000000
--- a/riscv/insns/mfc0.h
+++ /dev/null
@@ -1,28 +0,0 @@
-require_supervisor;
-
-switch(insn.rtype.rb)
-{
-  case 0:
-    RA = sext32(sr);
-    break;
-  case 1:
-    RA = sext32(epc);
-    break;
-  case 2:
-    RA = sext32(badvaddr);
-    break;
-  case 3:
-    RA = sext32(ebase);
-    break;
-
-  case 8:
-    RA = sext32(MEMSIZE >> 12);
-    break;
-
-  case 17:
-    RA = sext32(sim->get_fromhost());
-    break;
-
-  default:
-    RA = -1;
-}
diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
new file mode 100644
index 0000000..7808458
--- /dev/null
+++ b/riscv/insns/mfpcr.h
@@ -0,0 +1,29 @@
+require_supervisor;
+require64;
+
+switch(insn.rtype.rb)
+{
+  case 0:
+    RA = sr;
+    break;
+  case 1:
+    RA = epc;
+    break;
+  case 2:
+    RA = badvaddr;
+    break;
+  case 3:
+    RA = ebase;
+    break;
+
+  case 8:
+    RA = MEMSIZE >> 12;
+    break;
+
+  case 17:
+    RA = sim->get_fromhost();
+    break;
+
+  default:
+    RA = -1;
+}
diff --git a/riscv/insns/mtc0.h b/riscv/insns/mtc0.h
deleted file mode 100644
index ca593df..0000000
--- a/riscv/insns/mtc0.h
+++ /dev/null
@@ -1,18 +0,0 @@
-require_supervisor;
-
-switch(insn.rtype.rb)
-{
-  case 0:
-    set_sr(sext32(RA));
-    break;
-  case 1:
-    epc = sext32(RA);
-    break;
-  case 3:
-    ebase = sext32(RA & ~0xFFF);
-    break;
-
-  case 16:
-    sim->set_tohost(sext32(RA));
-    break;
-}
diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
new file mode 100644
index 0000000..67195a6
--- /dev/null
+++ b/riscv/insns/mtpcr.h
@@ -0,0 +1,19 @@
+require_supervisor;
+require64;
+
+switch(insn.rtype.rb)
+{
+  case 0:
+    set_sr(RA);
+    break;
+  case 1:
+    epc = RA;
+    break;
+  case 3:
+    ebase = RA & ~0xFFF;
+    break;
+
+  case 16:
+    sim->set_tohost(RA);
+    break;
+}
diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index d999172..9c81285 100644
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
-RC = sext32(RA * RB);
-
+require64;
+RC = RA * RB;
diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 90a17be..2d7ca4c 100644
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,2 +1,4 @@
-RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
-
+require64;
+int64_t rb = RA;
+int64_t ra = RB;
+RC = (int128_t(rb) * int128_t(ra)) >> 64;
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 9f3de3f..45e9704 100644
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,2 +1,2 @@
-RC = sext32((RA * RB) >> 32);
-
+require64;
+RC = (uint128_t(RA) * uint128_t(RB)) >> 64;
diff --git a/riscv/insns/mulhuw.h b/riscv/insns/mulhuw.h
new file mode 100644
index 0000000..9f3de3f
--- /dev/null
+++ b/riscv/insns/mulhuw.h
@@ -0,0 +1,2 @@
+RC = sext32((RA * RB) >> 32);
+
diff --git a/riscv/insns/mulhw.h b/riscv/insns/mulhw.h
new file mode 100644
index 0000000..90a17be
--- /dev/null
+++ b/riscv/insns/mulhw.h
@@ -0,0 +1,2 @@
+RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
+
diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
new file mode 100644
index 0000000..d999172
--- /dev/null
+++ b/riscv/insns/mulw.h
@@ -0,0 +1,2 @@
+RC = sext32(RA * RB);
+
diff --git a/riscv/insns/mwfpcr.h b/riscv/insns/mwfpcr.h
new file mode 100644
index 0000000..8a0a84a
--- /dev/null
+++ b/riscv/insns/mwfpcr.h
@@ -0,0 +1,28 @@
+require_supervisor;
+
+switch(insn.rtype.rb)
+{
+  case 0:
+    RA = sext32(sr);
+    break;
+  case 1:
+    RA = sext32(epc);
+    break;
+  case 2:
+    RA = sext32(badvaddr);
+    break;
+  case 3:
+    RA = sext32(ebase);
+    break;
+
+  case 8:
+    RA = sext32(MEMSIZE >> 12);
+    break;
+
+  case 17:
+    RA = sext32(sim->get_fromhost());
+    break;
+
+  default:
+    RA = -1;
+}
diff --git a/riscv/insns/mwtpcr.h b/riscv/insns/mwtpcr.h
new file mode 100644
index 0000000..ca593df
--- /dev/null
+++ b/riscv/insns/mwtpcr.h
@@ -0,0 +1,18 @@
+require_supervisor;
+
+switch(insn.rtype.rb)
+{
+  case 0:
+    set_sr(sext32(RA));
+    break;
+  case 1:
+    epc = sext32(RA);
+    break;
+  case 3:
+    ebase = sext32(RA & ~0xFFF);
+    break;
+
+  case 16:
+    sim->set_tohost(sext32(RA));
+    break;
+}
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 1bb3051..dfece43 100644
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA) % int32_t(RB));
-
+require64;
+RC = sreg_t(RA) % sreg_t(RB);
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index d028488..e8ee6b1 100644
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA) % uint32_t(RB));
-
+require64;
+RC = RA % RB;
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
new file mode 100644
index 0000000..d028488
--- /dev/null
+++ b/riscv/insns/remuw.h
@@ -0,0 +1,2 @@
+RC = sext32(uint32_t(RA) % uint32_t(RB));
+
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
new file mode 100644
index 0000000..1bb3051
--- /dev/null
+++ b/riscv/insns/remw.h
@@ -0,0 +1,2 @@
+RC = sext32(int32_t(RA) % int32_t(RB));
+
diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 67e6809..a07e038 100644
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1 +1,2 @@
-RC = sext32(RB << SHAMT);
+require64;
+RC = RB << SHAMT;
diff --git a/riscv/insns/sll32.h b/riscv/insns/sll32.h
new file mode 100644
index 0000000..cfd9ba3
--- /dev/null
+++ b/riscv/insns/sll32.h
@@ -0,0 +1,2 @@
+require64;
+RC = RB << (32+SHAMT);
diff --git a/riscv/insns/sllv.h b/riscv/insns/sllv.h
index f694a2f..7e81e6b 100644
--- a/riscv/insns/sllv.h
+++ b/riscv/insns/sllv.h
@@ -1 +1,2 @@
-RC = sext32(RB << (RA & 0x1F));
+require64;
+RC = RB << (RA & 0x3F);
diff --git a/riscv/insns/sllvw.h b/riscv/insns/sllvw.h
new file mode 100644
index 0000000..f694a2f
--- /dev/null
+++ b/riscv/insns/sllvw.h
@@ -0,0 +1 @@
+RC = sext32(RB << (RA & 0x1F));
diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
new file mode 100644
index 0000000..67e6809
--- /dev/null
+++ b/riscv/insns/sllw.h
@@ -0,0 +1 @@
+RC = sext32(RB << SHAMT);
diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index c2decb9..19118f0 100644
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1,2 @@
-RC = sext32(sreg_t(RB) >> SHAMT);
+require64;
+RC = sreg_t(RB) >> SHAMT;
diff --git a/riscv/insns/sra32.h b/riscv/insns/sra32.h
new file mode 100644
index 0000000..001e3bd
--- /dev/null
+++ b/riscv/insns/sra32.h
@@ -0,0 +1,2 @@
+require64;
+RC = sreg_t(RB) >> (32+SHAMT);
diff --git a/riscv/insns/srav.h b/riscv/insns/srav.h
index 8e9aa88..ec6fee8 100644
--- a/riscv/insns/srav.h
+++ b/riscv/insns/srav.h
@@ -1 +1,2 @@
-RC = sext32(sreg_t(RB) >> (RA & 0x1F));
+require64;
+RC = RB >> (RA & 0x3F);
diff --git a/riscv/insns/sravw.h b/riscv/insns/sravw.h
new file mode 100644
index 0000000..8e9aa88
--- /dev/null
+++ b/riscv/insns/sravw.h
@@ -0,0 +1 @@
+RC = sext32(sreg_t(RB) >> (RA & 0x1F));
diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
new file mode 100644
index 0000000..c2decb9
--- /dev/null
+++ b/riscv/insns/sraw.h
@@ -0,0 +1 @@
+RC = sext32(sreg_t(RB) >> SHAMT);
diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index 0537a1c..47426b1 100644
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1 +1,2 @@
-RC = sext32(RB >> SHAMT);
+require64;
+RC = RB >> SHAMT;
diff --git a/riscv/insns/srl32.h b/riscv/insns/srl32.h
new file mode 100644
index 0000000..5d52dea
--- /dev/null
+++ b/riscv/insns/srl32.h
@@ -0,0 +1,2 @@
+require64;
+RC = RB >> (32+SHAMT);
diff --git a/riscv/insns/srlv.h b/riscv/insns/srlv.h
index 7e1755f..ec6fee8 100644
--- a/riscv/insns/srlv.h
+++ b/riscv/insns/srlv.h
@@ -1 +1,2 @@
-RC = sext32(RB >> (RA & 0x1F));
+require64;
+RC = RB >> (RA & 0x3F);
diff --git a/riscv/insns/srlvw.h b/riscv/insns/srlvw.h
new file mode 100644
index 0000000..7e1755f
--- /dev/null
+++ b/riscv/insns/srlvw.h
@@ -0,0 +1 @@
+RC = sext32(RB >> (RA & 0x1F));
diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
new file mode 100644
index 0000000..0537a1c
--- /dev/null
+++ b/riscv/insns/srlw.h
@@ -0,0 +1 @@
+RC = sext32(RB >> SHAMT);
diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 60bcf27..e7ac407 100644
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1,2 @@
-RC = sext32(RA - RB);
-
+require64;
+RC = RA - RB;
diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
new file mode 100644
index 0000000..60bcf27
--- /dev/null
+++ b/riscv/insns/subw.h
@@ -0,0 +1,2 @@
+RC = sext32(RA - RB);
+