From: Jordi Vaquero <jordi.vaquero@metempsy.com>
Date: Tue, 23 Jun 2020 09:27:35 +0000 (+0200)
Subject: arch-arm: Add Check for AddressSize Fault
X-Git-Tag: v20.1.0.0~505
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6002f733cce64b81434c726dff080c5f1bf85827;p=gem5.git

arch-arm: Add Check for AddressSize Fault

This patch add a check for AddressSize Fault during translation when
MMU is disabled.

Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30619
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
---

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f92f8e00d..f007f9317 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1011,12 +1011,30 @@ TLB::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
         TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format)
 {
     bool is_fetch  = (mode == Execute);
+    bool is_atomic = req->isAtomic();
     req->setPaddr(vaddr);
     // When the MMU is off the security attribute corresponds to the
     // security state of the processor
     if (isSecure)
         req->setFlags(Request::SECURE);
 
+    bool selbit = bits(vaddr, 55);
+    TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+    int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+    int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+    if (addr_sz != 0){
+        Fault f;
+        if (is_fetch)
+            f = std::make_shared<PrefetchAbort>(vaddr,
+                ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+        else
+            f = std::make_shared<DataAbort>( vaddr,
+                TlbEntry::DomainType::NoAccess,
+                is_atomic ? false : mode==Write,
+                ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+        return f;
+    }
+
     // @todo: double check this (ARM ARM issue C B3.2.1)
     if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 ||
         nmrr.or0 == 0 || prrr.tr0 != 0x2) {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 04403fc5f..b61fc2020 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -237,7 +237,7 @@ Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
                       bool isInstr);
 int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
-               TTBCR tcr, ExceptionLevel el);
+               TCR tcr, ExceptionLevel el);
 
 static inline bool
 inSecureState(SCR scr, CPSR cpsr)