From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 3 Oct 2014 08:04:15 +0000 (+0200)
Subject: remove buffers in opt_clean
X-Git-Tag: yosys-0.4~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=600c6cb013b6cf872f3b3f01c7d88df2092e84d9;p=yosys.git

remove buffers in opt_clean
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 0e5ed238f..15bbf54e0 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -293,6 +293,19 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
 	if (verbose)
 		log("Finding unused cells or wires in module %s..\n", module->name.c_str());
 
+	std::vector<RTLIL::Cell*> delcells;
+	for (auto cell : module->cells())
+		if (cell->type == "$pos") {
+			bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+			RTLIL::SigSpec a = cell->getPort("\\A");
+			RTLIL::SigSpec y = cell->getPort("\\Y");
+			a.extend_u0(SIZE(y), is_signed);
+			module->connect(y, a);
+			delcells.push_back(cell);
+		}
+	for (auto cell : delcells)
+		module->remove(cell);
+
 	rmunused_module_cells(module, verbose);
 	rmunused_module_signals(module, purge_mode, verbose);
 }