From: lkcl <lkcl@web>
Date: Wed, 12 Apr 2023 21:57:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls010_v1~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6021eb9f0f268e0efa0f9f39358d3f27fa7ad01e;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index b4dbea506..eb97a96bf 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -89,6 +89,30 @@ revisions.  Compliancy Subsets exist to ensure minimum levels of binary
 interoperability expectations within certain environments.  Details in
 the [[svp64/appendix]].
 
+## Strict Program Order
+
+Many Vector ISAs allow interrupts to occur in the middle of
+processing of large Vector operations, only under the condition
+that continuation on return will restart the entire operation.
+The reason is that saving of full Architectural State is
+not practical.
+
+Simple-V operates on an entirely different paradigm from traditional
+Vector ISAs: as a Sub-Program Counter where "Elements" are synonymous
+with Scalar instructions. With this in mind it is critical for
+implementations to observe Strict Element-Level Program Order.
+Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
+but the full SVP64 Architectural State may be saved and
+restored through manual copying of `SVSTATE` and the four
+REMAP SPRs.
+This capability also allows nested function calls to be made from
+inside Vector loops, which is unusual for Vector ISAs.
+
+Strict Program Order is also preserved by the Parallel Reduction
+REMAP Schedule, but only at the cost of requiring the destination
+Vector to be permitted to store partial progress of the Deterministic
+Parallel Reduction Schedule.
+
 ## SVP64 encoding features
 
 A number of features need to be compacted into a very small space of