From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 22 Aug 2018 21:07:45 +0000 (-0700)
Subject: Make IRQ_COP read-only/undelegable unless coprocessor is present
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60235e3816220eabc6f6e48d103889300d5547df;p=riscv-isa-sim.git

Make IRQ_COP read-only/undelegable unless coprocessor is present
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8bcd8e2..4a7d0ec 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -330,7 +330,8 @@ int processor_t::paddr_bits()
 void processor_t::set_csr(int which, reg_t val)
 {
   val = zext_xlen(val);
-  reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
+  reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
+                       | ((ext != NULL) << IRQ_COP);
   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
   switch (which)
   {