From: Florent Kermarrec Date: Wed, 24 Sep 2014 11:56:12 +0000 (+0200) Subject: manage clock domain crossing and data width conversion in gtx X-Git-Tag: 24jan2021_ls180~2572^2~201 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60324295faecabb84dba28979e5014e5ae62fa6f;p=litex.git manage clock domain crossing and data width conversion in gtx --- diff --git a/lib/sata/k7sataphy/gtx.py b/lib/sata/k7sataphy/gtx.py index a4ebbb48..a653eb64 100644 --- a/lib/sata/k7sataphy/gtx.py +++ b/lib/sata/k7sataphy/gtx.py @@ -1,4 +1,6 @@ from migen.fhdl.std import * +from migen.actorlib.fifo import AsyncFIFO +from migen.actorlib.structuring import Converter from lib.sata.k7sataphy.std import * @@ -27,7 +29,6 @@ class GTXE2_CHANNEL(Module): self.rxuserrdy = Signal() # Receive Ports - 8b10b Decoder - self.rxcharisk = Signal(2) self.rxdisperr = Signal(2) self.rxnotintable = Signal(2) @@ -37,7 +38,6 @@ class GTXE2_CHANNEL(Module): # Receive Ports - RX Data Path interface self.gtrxreset = Signal() - self.rxdata = Signal(16) self.rxoutclk = Signal() self.rxusrclk = Signal() self.rxusrclk2 = Signal() @@ -68,7 +68,6 @@ class GTXE2_CHANNEL(Module): self.txuserrdy = Signal() # Transmit Ports - 8b10b Encoder Control Ports - self.txcharisk = Signal(2) # Transmit Ports - TX Buffer and Phase Alignment Ports self.txdlyen = Signal() @@ -83,7 +82,6 @@ class GTXE2_CHANNEL(Module): # Transmit Ports - TX Data Path interface self.gttxreset = Signal() - self.txdata = Signal() self.txoutclk = Signal() self.txoutclkfabric = Signal() self.txoutclkpcs = Signal() @@ -126,6 +124,9 @@ class GTXE2_CHANNEL(Module): rxdata = Signal(16) rxcharisk = Signal(2) + txdata = Signal(16) + txcharisk = Signal(2) + self.specials += \ Instance("GTXE2_CHANNEL", # Simulation-Only Attributes @@ -765,18 +766,68 @@ class GTXE2_CHANNEL(Module): # realign rxdata / rxcharisk rxdata_r = Signal(dw) rxcharisk_r = Signal(dw//8) + rxdata_aligned = Signal(dw) + rxcharisk_aligned = Signal(dw//8) self.sync.sata_rx += [ rxdata_r.eq(rxdata), rxcharisk_r.eq(rxcharisk) ] cases = {} cases[1<<0] = [ - self.rxdata.eq(rx_data_r[0:dw]), - self.rxcharisk.eq(rx_charisk_r[0:dw//8]) + rxdata_aligned .eq(rx_data_r[0:dw]), + rxcharisk_aligned .eq(rx_charisk_r[0:dw//8]) ] for i in range(1, dw//8): cases[1<