From: lkcl <lkcl@web>
Date: Fri, 16 Sep 2022 10:03:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~406
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6056244fa0f686229dffa6f6e1b0b5bbfd409d37;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index d958e41a8..459b3bedf 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -69,8 +69,18 @@ Branch.
 
 # Basic principle
 
-The basic principle of Simple-V is to provide a Precise-Interruptible
-Zero-Overhead Loop system with associated register "offsetting"
+The inspiration for this came from the fact that on examination of every
+Vector ISA pseudocode encountered the Vector operations were expressed
+as a for-loop on a Scalar element
+operation, and then both a Scalar **and** a Vector instruction was added.
+It felt natural to separate the two at both the ISA and the Hardware Level
+and thus provide only Scalar instructions (instantly halving the number
+of instructions), leaving it up to implementors
+to implement Superscalar and Multi-Issue Micro-architectures at their
+discretion.
+
+Thus the basic principle of Simple-V is to provide a Precise-Interruptible
+Zero-Overhead Loop system[^zolc] with associated register "offsetting"
 which augments a Suffixed instruction as a "template",
 incrementing the register numbering progressively *and automatically*
 each time round the "loop".  Thus it may be considered to be a form
@@ -84,16 +94,6 @@ Micro-architectural capabilities much more comprehensive festures are
 easy to add, working up towards an ISA that easily matches the capability
 of powerful 3D GPU Vector Supercomputing ISAs, without ever adding even
 one single Vector opcode.
-The inspiration for this came from the fact that on examination of every
-Vector ISA pseudocode encountered the Vector operations were expressed
-as a for-loop on a Scalar element
-operation, and then both a Scalar **and** a Vector instruction was added.
-
-It felt natural to separate the two at both the ISA and the Hardware Level
-and thus provide only Scalar instructions (instantly halving the number
-of instructions), leaving it up to implementors
-to implement Superscalar and Multi-Issue Micro-architectures at their
-discretion.
 
 # Extension Levels
 
@@ -1077,6 +1077,7 @@ operations.
 
 [[!tag opf_rfc]]
 
+[^zolc]: first introduced in DSPs, Zero-Overhead Loops are astoundingly effective in reducing total number of instructions executed or needed. [ZOLC](https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.301.4646&rep=rep1&type=pdf) reduces instructions by **25 to 80 percent**.
 [^msr]: an MSR bit or bits, conceptually equivalent to `MSR.SF` and added for the same reasons, would suffice perfectly.
 [^extend]: Prefix opcode space (or MSR bits) **must** be reserved in advance to do so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2
 [^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact SVP64-single still embeds v3.0 Scalar operations.