From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Sep 2020 13:10:02 +0000 (+0100)
Subject: remove the gpio peripheral which was previously hard-linked to interrupts
X-Git-Tag: semi_working_ecp5~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6061aec69b5f26ec644d53df8588fb44b6699ce3;p=soc.git

remove the gpio peripheral which was previously hard-linked to interrupts
---

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index dd416ee8..aae1966e 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -5,7 +5,7 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 from litex.soc.interconnect import wishbone as wb
 from litex.soc.cores.cpu import CPU
 
-CPU_VARIANTS = ["standard", "standard32"]
+CPU_VARIANTS = ["standard", "standard32", "ls180"]
 
 
 def make_wb_bus(prefix, obj):
@@ -63,7 +63,9 @@ class LibreSoC(CPU):
 
         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
-        self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
+
+        if variant != "ls180":
+            self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
 
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
@@ -106,7 +108,8 @@ class LibreSoC(CPU):
         self.cpu_params.update(make_wb_bus("dbus_", dbus))
         self.cpu_params.update(make_wb_bus("ics_wb_", ics))
         self.cpu_params.update(make_wb_bus("icp_wb_", icp))
-        self.cpu_params.update(make_wb_bus("gpio_wb_", gpio))
+        if variant != "ls180":
+            self.cpu_params.update(make_wb_bus("gpio_wb_", gpio))
 
         # add verilog sources
         self.add_sources(platform)
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index cdbcef13..67f87fde 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -63,10 +63,7 @@ class LibreSoCSim(SoCCore):
         #cpu_data_width = 32
         cpu_data_width = 64
 
-        if cpu_data_width == 32:
-            variant = "standard32"
-        else:
-            variant = "standard"
+        variant = "ls180"
 
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
@@ -86,7 +83,6 @@ class LibreSoCSim(SoCCore):
         # reserve XICS ICP and XICS memory addresses.
         self.mem_map['icp']  = 0xc0010000
         self.mem_map['ics']  = 0xc0011000
-        self.mem_map['gpio'] = 0xc0012000
         #self.csr_map["icp"] = 8  #  8 x 0x800 == 0x4000
         #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
 
@@ -127,7 +123,7 @@ class LibreSoCSim(SoCCore):
             integrated_main_ram_size = 0x00000000 if with_sdram \
                                         else 0x10000000 , # 256MB
             )
-        self.platform.name = "sim"
+        self.platform.name = "ls180"
 
         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
@@ -146,13 +142,6 @@ class LibreSoCSim(SoCCore):
             ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 
-            # Simple GPIO peripheral
-            gpio_addr = self.mem_map['gpio']
-            gpio_wb = self.cpu.simple_gpio
-            gpio_region = SoCRegion(origin=gpio_addr, size=0x20, cached=False)
-            self.bus.add_slave(name='gpio', slave=gpio_wb, region=gpio_region)
-
-
         # CRG -----------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))
 
diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index b93d47c2..8cd713f8 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,7 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
-                         gpio=True, # for test purposes
+                         gpio=False, # for test purposes
                          units=units)
 
     dut = TestIssuer(pspec)