From: Eric Anholt <eric@anholt.net>
Date: Wed, 25 Oct 2017 02:13:17 +0000 (-0700)
Subject: broadcom/vc5: Drop alignment bits from Z/S rendering mode config address.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=607031f411cfef1c80a4088f16a5bc33d995849c;p=mesa.git

broadcom/vc5: Drop alignment bits from Z/S rendering mode config address.

Improves CLIF dumping output.
---

diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 86fc8102145..3be33f41a08 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -528,7 +528,7 @@
   </packet>
 
   <packet code="121" name="Tile Rendering Mode Configuration (Z/Stencil config)" cl="R">
-    <field name="Address" size="32" start="32" type="address"/>
+    <field name="Address" size="26" start="38" type="address"/>
 
     <field name="Padded height of output image in UIF blocks" size="13" start="25" type="uint"/>