From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Nov 2021 19:13:24 +0000 (+0000)
Subject: truncate CR regspec_decode_write reg mask to 8 bit
X-Git-Tag: sv_maxu_works-initial~735
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6089d8f0c4cd7dbb48bfcddb5bc487c7047abaf4;p=openpower-isa.git

truncate CR regspec_decode_write reg mask to 8 bit
---

diff --git a/src/openpower/decoder/power_regspec_map.py b/src/openpower/decoder/power_regspec_map.py
index a7f150ec..5ec5f629 100644
--- a/src/openpower/decoder/power_regspec_map.py
+++ b/src/openpower/decoder/power_regspec_map.py
@@ -145,7 +145,7 @@ def regspec_decode_write(e, regfile, name):
         if name == 'full_cr': # full CR (from FXM field)
             return e.do.write_cr_whole.ok, e.do.write_cr_whole.data
         if name == 'cr_a': # CR A
-            return e.write_cr.ok, 1<<(7-e.write_cr.data)
+            return e.write_cr.ok, (1<<(7-e.write_cr.data))[0:8]
 
     # XER regfile