From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 Jun 2018 05:32:40 +0000 (+0100)
Subject: add DDR link
X-Git-Tag: convert-csv-opcode-to-binary~5190
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=608ce98a004c001a89fa597eb15a69b361943857;p=libreriscv.git

add DDR link
---

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 6dc5420d4..9f96863e4 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -217,7 +217,7 @@ TBD
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
 * 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging
 
 Some interfaces at:
@@ -235,6 +235,7 @@ Some interfaces at:
 List of Interfaces:
 
 * [[CSI]]
+* [[DDR]]
 * [[JTAG]]
 * [[I2C]]
 * [[I2S]]