From: lkcl <lkcl@web>
Date: Sun, 21 May 2023 12:44:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=608d5b487f065a64fc3b0bae9ab63bd0fe693aea;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 5b497a31b..926e3b625 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -78,7 +78,7 @@ modes make sense:
 * simple (no augmentation)
 * Fault-first (where Vector Indexed is banned)
 * Data-dependent Fail-First (extremely useful for Linked-List pointer-chasing)
-* Signed Effective Address computation (Vector Indexed only)
+* Signed Effective Address computation (Vector Indexed only, on RB)
 
 More than that however it is necessary to fit the usual Vector ISA
 capabilities onto both Power ISA LD/ST with immediate and to LD/ST