From: Richard Sandiford Date: Mon, 30 Sep 2002 12:04:54 +0000 (+0000) Subject: [gas/] X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60b63b728f8bd4156ee67f70183fa01b425c2cba;p=binutils-gdb.git [gas/] * doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181, vr5400 and vr5500. Add entry for -mfix-vr4122-bugs. * config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros. (hilo_interlocks): True for CPU_VR5500. (gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500. (mips_fix_vr4122_bugs): New. (append_insn): Work around 4122 errors if mips_fix_vr4122_bugs. (mips_emit_delays): Likewise. (macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR. [M_ROLI]: Likewise ror if CPU_HAS_ROR. (validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'. (OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options. (md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs. (OPTION_ELF_BASE): Bump. (md_parse_option): Handle the new options. (mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181, vr5400 and vr5500. [gas/testsuite/] * gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to... * gas/mips/vr4111.[sd]: ...this new test. * gas/mips/vr4120.[sd], * gas/mips/vr4122.[sd], * gas/mips/vr5400.[sd], * gas/mips/vr5500.[sd]: New tests. * mips.exp: Run them. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 13ed1e8545a..ec821c65ba6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,29 @@ +2002-09-30 Gavin Romig-Koch + Ken Raeburn + Aldy Hernandez + DJ Delorie + Michael Meissner + Eric Christopher + Richard Sandiford + + * doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181, + vr5400 and vr5500. Add entry for -mfix-vr4122-bugs. + * config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros. + (hilo_interlocks): True for CPU_VR5500. + (gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500. + (mips_fix_vr4122_bugs): New. + (append_insn): Work around 4122 errors if mips_fix_vr4122_bugs. + (mips_emit_delays): Likewise. + (macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR. + [M_ROLI]: Likewise ror if CPU_HAS_ROR. + (validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'. + (OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options. + (md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs. + (OPTION_ELF_BASE): Bump. + (md_parse_option): Handle the new options. + (mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181, + vr5400 and vr5500. + 2002-09-29 H.J. Lu * config/tc-mips.c (md_apply_fix3): Subtract the symbol value diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 7c8be079a60..d88c9257530 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -296,11 +296,18 @@ static int mips_32bitmode = 0; #define CPU_HAS_MDMX(cpu) (false \ ) +/* True if CPU has a dror instruction. */ +#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) + +/* True if CPU has a ror instruction. */ +#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) + /* Whether the processor uses hardware interlocks to protect reads from the HI and LO registers, and thus does not require nops to be inserted. */ #define hilo_interlocks (mips_arch == CPU_R4010 \ + || mips_arch == CPU_VR5500 \ || mips_arch == CPU_SB1 \ ) @@ -308,12 +315,16 @@ static int mips_32bitmode = 0; from the GPRs, and thus does not require nops to be inserted. */ #define gpr_interlocks \ (mips_opts.isa != ISA_MIPS1 \ + || mips_arch == CPU_VR5400 \ + || mips_arch == CPU_VR5500 \ || mips_arch == CPU_R3900) /* As with other "interlocks" this is used by hardware that has FP (co-processor) interlocks. */ /* Itbl support may require additional care here. */ #define cop_interlocks (mips_arch == CPU_R4300 \ + || mips_arch == CPU_VR5400 \ + || mips_arch == CPU_VR5500 \ || mips_arch == CPU_SB1 \ ) @@ -550,6 +561,8 @@ static const unsigned int mips16_to_32_reg_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + +static int mips_fix_4122_bugs; /* Since the MIPS does not have multiple forms of PC relative instructions, we do not have to do relaxing as is done on other @@ -1689,6 +1702,50 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi) if (prev_prev_nop && nops == 0) ++nops; + if (mips_fix_4122_bugs && prev_insn.insn_mo->name) + { + /* We're out of bits in pinfo, so we must resort to string + ops here. Shortcuts are selected based on opcodes being + limited to the VR4122 instruction set. */ + int min_nops = 0; + const char *pn = prev_insn.insn_mo->name; + const char *tn = ip->insn_mo->name; + if (strncmp(pn, "macc", 4) == 0 + || strncmp(pn, "dmacc", 5) == 0) + { + /* Errata 21 - [D]DIV[U] after [D]MACC */ + if (strstr (tn, "div")) + { + min_nops = 1; + } + + /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ + if (pn[0] == 'd' /* dmacc */ + && (strncmp(tn, "dmult", 5) == 0 + || strncmp(tn, "dmacc", 5) == 0)) + { + min_nops = 1; + } + + /* Errata 24 - MT{LO,HI} after [D]MACC */ + if (strcmp (tn, "mtlo") == 0 + || strcmp (tn, "mthi") == 0) + { + min_nops = 1; + } + + } + else if (strncmp(pn, "dmult", 5) == 0 + && (strncmp(tn, "dmult", 5) == 0 + || strncmp(tn, "dmacc", 5) == 0)) + { + /* Here is the rest of errata 23. */ + min_nops = 1; + } + if (nops < min_nops) + nops = min_nops; + } + /* If we are being given a nop instruction, don't bother with one of the nops we would otherwise output. This will only happen when a nop instruction is used with mips_optimize set @@ -2586,6 +2643,20 @@ mips_emit_delays (insns) ++nops; } + if (mips_fix_4122_bugs && prev_insn.insn_mo->name) + { + int min_nops = 0; + const char *pn = prev_insn.insn_mo->name; + if (strncmp(pn, "macc", 4) == 0 + || strncmp(pn, "dmacc", 5) == 0 + || strncmp(pn, "dmult", 5) == 0) + { + min_nops = 1; + } + if (nops < min_nops) + nops = min_nops; + } + if (nops > 0) { struct insn_label_list *l; @@ -6714,6 +6785,17 @@ macro2 (ip) if (imm_expr.X_op != O_constant) as_bad (_("rotate count too large")); rot = imm_expr.X_add_number & 0x3f; + if (CPU_HAS_DROR (mips_arch)) + { + rot = (64 - rot) & 0x3f; + if (rot >= 32) + macro_build ((char *) NULL, &icnt, NULL, "dror32", + "d,w,<", dreg, sreg, rot - 32); + else + macro_build ((char *) NULL, &icnt, NULL, "dror", + "d,w,<", dreg, sreg, rot); + break; + } if (rot == 0) macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", "d,w,<", dreg, sreg, 0); @@ -6741,6 +6823,12 @@ macro2 (ip) if (imm_expr.X_op != O_constant) as_bad (_("rotate count too large")); rot = imm_expr.X_add_number & 0x1f; + if (CPU_HAS_ROR (mips_arch)) + { + macro_build ((char *) NULL, &icnt, NULL, "ror", + "d,w,<", dreg, sreg, (32 - rot) & 0x1f); + break; + } if (rot == 0) macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", dreg, sreg, 0); @@ -7716,6 +7804,10 @@ validate_mips_insn (opc) case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); USE_BITS (OP_MASK_RT, OP_SH_RT); break; + case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; + case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; + case '[': break; + case ']': break; default: as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), c, opc->name, opc->args); @@ -7907,6 +7999,8 @@ mips_ip (str, ip) return; case ')': /* these must match exactly */ + case '[': + case ']': if (*s++ == *args) continue; break; @@ -8828,6 +8922,41 @@ mips_ip (str, ip) ip->insn_opcode |= c; continue; + case 'e': + /* Must be at least one digit. */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + + if ((unsigned long) imm_expr.X_add_number + > (unsigned long) OP_MASK_VECBYTE) + { + as_bad (_("bad byte vector index (%ld)"), + (long) imm_expr.X_add_number); + imm_expr.X_add_number = 0; + } + + ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case '%': + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + + if ((unsigned long) imm_expr.X_add_number + > (unsigned long) OP_MASK_VECALIGN) + { + as_bad (_("bad byte vector index (%ld)"), + (long) imm_expr.X_add_number); + imm_expr.X_add_number = 0; + } + + ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + default: as_bad (_("bad char = '%c'\n"), *args); internalError (); @@ -9992,8 +10121,12 @@ struct option md_longopts[] = {"mdmx", no_argument, NULL, OPTION_MDMX}, #define OPTION_NO_MDMX (OPTION_MD_BASE + 36) {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, +#define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37) +#define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38) + {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, + {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, #ifdef OBJ_ELF -#define OPTION_ELF_BASE (OPTION_MD_BASE + 37) +#define OPTION_ELF_BASE (OPTION_MD_BASE + 39) #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, @@ -10194,6 +10327,14 @@ md_parse_option (c, arg) g_switch_value = 0x7fffffff; break; + case OPTION_FIX_VR4122: + mips_fix_4122_bugs = 1; + break; + + case OPTION_NO_FIX_VR4122: + mips_fix_4122_bugs = 0; + break; + #ifdef OBJ_ELF /* When generating ELF code, we permit -KPIC and -call_shared to select SVR4_PIC, and -non_shared to select no PIC. This is @@ -13644,6 +13785,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "r4010", 0, ISA_MIPS2, CPU_R4010 }, { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, + { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, + { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, + { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, { "r4400", 0, ISA_MIPS3, CPU_R4400 }, { "r4600", 0, ISA_MIPS3, CPU_R4600 }, @@ -13655,6 +13799,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "r10000", 0, ISA_MIPS4, CPU_R10000 }, { "r12000", 0, ISA_MIPS4, CPU_R12000 }, { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, + { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, + { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index b19c09b3b0c..6b82fd0c957 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -116,6 +116,12 @@ This tells the assembler to accept MDMX instructions. Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mfix-vr4122-bugs +@itemx -no-mfix-vr4122-bugs +Insert @samp{nop} instructions to avoid errors in certain versions of +the vr4122 core. This option is intended to be used on GCC-generated +code: it is not designed to catch errors in hand-written assembler code. + @item -m4010 @itemx -no-m4010 Generate code for the LSI @sc{r4010} chip. This tells the assembler to @@ -152,6 +158,9 @@ understood. Valid @var{cpu} value are: 4010, 4100, 4111, +vr4120, +vr4130, +vr4181, 4300, 4400, 4600, @@ -162,6 +171,8 @@ rm5230, rm5231, rm5261, rm5721, +vr5400, +vr5500, 6000, rm7000, 8000, diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 1336d7d6921..e2ac1236b9b 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,19 @@ +2002-09-30 Gavin Romig-Koch + Ken Raeburn + Aldy Hernandez + DJ Delorie + Michael Meissner + Eric Christopher + Richard Sandiford + + * gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to... + * gas/mips/vr4111.[sd]: ...this new test. + * gas/mips/vr4120.[sd], + * gas/mips/vr4122.[sd], + * gas/mips/vr5400.[sd], + * gas/mips/vr5500.[sd]: New tests. + * mips.exp: Run them. + 2002-09-27 Kaz Kojima * gas/sh/pcrel2.s: New. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index aef19083114..c5bd38b9af9 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -153,6 +153,11 @@ if { [istarget mips*-*-*] } then { run_dump_test "mips4010" run_dump_test "mips4650" run_dump_test "mips4100" + run_dump_test "vr4111" + run_dump_test "vr4120" + run_dump_test "vr4122" + run_dump_test "vr5400" + run_dump_test "vr5500" run_dump_test "perfcount" run_dump_test "lineno" run_dump_test "sync" diff --git a/gas/testsuite/gas/mips/mips4100.d b/gas/testsuite/gas/mips/mips4100.d index 4ef2e193423..9c0c673eae5 100644 --- a/gas/testsuite/gas/mips/mips4100.d +++ b/gas/testsuite/gas/mips/mips4100.d @@ -6,10 +6,7 @@ .*: +file format .*mips.* Disassembly of section \.text: -0+0000 dmadd16 a0,a1 - ... -0+000c madd16 a1,a2 -0+0010 hibernate -0+0014 standby -0+0018 suspend -0+001c nop +0+0000 hibernate +0+0004 standby +0+0008 suspend +0+000c nop diff --git a/gas/testsuite/gas/mips/mips4100.s b/gas/testsuite/gas/mips/mips4100.s index b60db9626de..42ae5776b3f 100644 --- a/gas/testsuite/gas/mips/mips4100.s +++ b/gas/testsuite/gas/mips/mips4100.s @@ -2,8 +2,6 @@ stuff: .ent stuff - dmadd16 $4,$5 - madd16 $5,$6 hibernate standby suspend diff --git a/gas/testsuite/gas/mips/vr4111.d b/gas/testsuite/gas/mips/vr4111.d new file mode 100644 index 00000000000..6c8d4457721 --- /dev/null +++ b/gas/testsuite/gas/mips/vr4111.d @@ -0,0 +1,11 @@ +#objdump: -dr +#name: MIPS VR4111 +#as: -march=vr4111 + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+000 <\.text>: + + 0: 00850029 dmadd16 a0,a1 + \.\.\. + + c: 00a60028 madd16 a1,a2 diff --git a/gas/testsuite/gas/mips/vr4111.s b/gas/testsuite/gas/mips/vr4111.s new file mode 100644 index 00000000000..0a2ffc66b21 --- /dev/null +++ b/gas/testsuite/gas/mips/vr4111.s @@ -0,0 +1,2 @@ + dmadd16 $4,$5 + madd16 $5,$6 diff --git a/gas/testsuite/gas/mips/vr4120.d b/gas/testsuite/gas/mips/vr4120.d new file mode 100644 index 00000000000..7c9bcd9a30d --- /dev/null +++ b/gas/testsuite/gas/mips/vr4120.d @@ -0,0 +1,29 @@ +#objdump: -dr +#name: MIPS VR4120 +#as: -march=vr4120 + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+000 <\.text>: + + 0: 00002012 mflo a0 + \.\.\. + + c: 00a62029 dmacc a0,a1,a2 + +10: 00a62229 dmacchi a0,a1,a2 + +14: 00a62629 dmacchis a0,a1,a2 + +18: 00a62269 dmacchiu a0,a1,a2 + +1c: 00a62669 dmacchius a0,a1,a2 + +20: 00a62429 dmaccs a0,a1,a2 + +24: 00a62069 dmaccu a0,a1,a2 + +28: 00a62469 dmaccus a0,a1,a2 + +2c: 00002012 mflo a0 + \.\.\. + +38: 00a62028 macc a0,a1,a2 + +3c: 00a62228 macchi a0,a1,a2 + +40: 00a62628 macchis a0,a1,a2 + +44: 00a62268 macchiu a0,a1,a2 + +48: 00a62668 macchius a0,a1,a2 + +4c: 00a62428 maccs a0,a1,a2 + +50: 00a62068 maccu a0,a1,a2 + +54: 00a62468 maccus a0,a1,a2 +#... diff --git a/gas/testsuite/gas/mips/vr4120.s b/gas/testsuite/gas/mips/vr4120.s new file mode 100644 index 00000000000..7550f9bfb27 --- /dev/null +++ b/gas/testsuite/gas/mips/vr4120.s @@ -0,0 +1,19 @@ + # Include mflos to check for nop insertion. + mflo $4 + dmacc $4,$5,$6 + dmacchi $4,$5,$6 + dmacchis $4,$5,$6 + dmacchiu $4,$5,$6 + dmacchius $4,$5,$6 + dmaccs $4,$5,$6 + dmaccu $4,$5,$6 + dmaccus $4,$5,$6 + mflo $4 + macc $4,$5,$6 + macchi $4,$5,$6 + macchis $4,$5,$6 + macchiu $4,$5,$6 + macchius $4,$5,$6 + maccs $4,$5,$6 + maccu $4,$5,$6 + maccus $4,$5,$6 diff --git a/gas/testsuite/gas/mips/vr4122.d b/gas/testsuite/gas/mips/vr4122.d new file mode 100644 index 00000000000..7c03a2d62ea --- /dev/null +++ b/gas/testsuite/gas/mips/vr4122.d @@ -0,0 +1,68 @@ +#objdump: -dz --prefix-addresses -m mips:4120 +#as: -march=vr4120 -mtune=vr4120 -mfix-vr4122-bugs +#name: MIPS vr4122 workarounds + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> macc a0,a1,a2 +0+0004 <[^>]*> nop +0+0008 <[^>]*> div zero,a3,t0 +0+000c <[^>]*> or a0,a0,a1 +0+0010 <[^>]*> dmacc a0,a1,a2 +0+0014 <[^>]*> nop +0+0018 <[^>]*> div zero,a3,t0 +0+001c <[^>]*> or a0,a0,a1 +0+0020 <[^>]*> macc a0,a1,a2 +0+0024 <[^>]*> nop +0+0028 <[^>]*> divu zero,a3,t0 +0+002c <[^>]*> or a0,a0,a1 +0+0030 <[^>]*> dmacc a0,a1,a2 +0+0034 <[^>]*> nop +0+0038 <[^>]*> divu zero,a3,t0 +0+003c <[^>]*> or a0,a0,a1 +0+0040 <[^>]*> macc a0,a1,a2 +0+0044 <[^>]*> nop +0+0048 <[^>]*> ddiv zero,a3,t0 +0+004c <[^>]*> or a0,a0,a1 +0+0050 <[^>]*> dmacc a0,a1,a2 +0+0054 <[^>]*> nop +0+0058 <[^>]*> ddiv zero,a3,t0 +0+005c <[^>]*> or a0,a0,a1 +0+0060 <[^>]*> macc a0,a1,a2 +0+0064 <[^>]*> nop +0+0068 <[^>]*> ddivu zero,a3,t0 +0+006c <[^>]*> or a0,a0,a1 +0+0070 <[^>]*> dmacc a0,a1,a2 +0+0074 <[^>]*> nop +0+0078 <[^>]*> ddivu zero,a3,t0 +0+007c <[^>]*> or a0,a0,a1 +0+0080 <[^>]*> dmult a0,a1 +0+0084 <[^>]*> nop +0+0088 <[^>]*> dmult a2,a3 +0+008c <[^>]*> or a0,a0,a1 +0+0090 <[^>]*> dmultu a0,a1 +0+0094 <[^>]*> nop +0+0098 <[^>]*> dmultu a2,a3 +0+009c <[^>]*> or a0,a0,a1 +0+00a0 <[^>]*> dmacc a0,a1,a2 +0+00a4 <[^>]*> nop +0+00a8 <[^>]*> dmacc a2,a3,t0 +0+00ac <[^>]*> or a0,a0,a1 +0+00b0 <[^>]*> dmult a0,a1 +0+00b4 <[^>]*> nop +0+00b8 <[^>]*> dmacc a2,a3,t0 +0+00bc <[^>]*> or a0,a0,a1 +0+00c0 <[^>]*> macc a0,a1,a2 +0+00c4 <[^>]*> nop +0+00c8 <[^>]*> mtlo a3 +0+00cc <[^>]*> dmacc a0,a1,a2 +0+00d0 <[^>]*> nop +0+00d4 <[^>]*> mtlo a3 +0+00d8 <[^>]*> macc a0,a1,a2 +0+00dc <[^>]*> nop +0+00e0 <[^>]*> mthi a3 +0+00e4 <[^>]*> dmacc a0,a1,a2 +0+00e8 <[^>]*> nop +0+00ec <[^>]*> mthi a3 +#... diff --git a/gas/testsuite/gas/mips/vr4122.s b/gas/testsuite/gas/mips/vr4122.s new file mode 100644 index 00000000000..6c38c885da1 --- /dev/null +++ b/gas/testsuite/gas/mips/vr4122.s @@ -0,0 +1,65 @@ +# Test that certain vr4122 hardware bugs are worked around. +# Note that we only work around bugs gcc may generate. + +r21: + macc $4,$5,$6 + div $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + div $0,$7,$8 + or $4,$5 + + macc $4,$5,$6 + divu $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + divu $0,$7,$8 + or $4,$5 + + macc $4,$5,$6 + ddiv $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + ddiv $0,$7,$8 + or $4,$5 + + macc $4,$5,$6 + ddivu $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + ddivu $0,$7,$8 + or $4,$5 + +r23: + dmult $4,$5 + dmult $6,$7 + or $4,$5 + + dmultu $4,$5 + dmultu $6,$7 + or $4,$5 + + dmacc $4,$5,$6 + dmacc $6,$7,$8 + or $4,$5 + + dmult $4,$5 + dmacc $6,$7,$8 + or $4,$5 + +r24: + macc $4,$5,$6 + mtlo $7 + + dmacc $4,$5,$6 + mtlo $7 + + macc $4,$5,$6 + mthi $7 + + dmacc $4,$5,$6 + mthi $7 diff --git a/gas/testsuite/gas/mips/vr5400.d b/gas/testsuite/gas/mips/vr5400.d new file mode 100644 index 00000000000..9d5d1eee19b --- /dev/null +++ b/gas/testsuite/gas/mips/vr5400.d @@ -0,0 +1,130 @@ +#objdump: -dr --prefix-addresses +#name: MIPS VR5400 +#as: -march=vr5400 + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 mul a0,a1,a2 +0+0004 mulu a0,a1,a2 +0+0008 mulhi a0,a1,a2 +0+000c mulhiu a0,a1,a2 +0+0010 muls a0,a1,a2 +0+0014 mulsu a0,a1,a2 +0+0018 mulshi a0,a1,a2 +0+001c mulshiu a0,a1,a2 +0+0020 macc a0,a1,a2 +0+0024 maccu a0,a1,a2 +0+0028 macchi a0,a1,a2 +0+002c macchiu a0,a1,a2 +0+0030 msac a0,a1,a2 +0+0034 msacu a0,a1,a2 +0+0038 msachi a0,a1,a2 +0+003c msachiu a0,a1,a2 +0+0040 ror a0,a1,0x19 +0+0044 rorv a0,a1,a2 +0+0048 dror a0,a1,0x19 +0+004c dror32 a0,a1,0x19 +0+0050 dror32 a0,a1,0x19 +0+0054 drorv a0,a1,a2 +0+0058 dbreak +0+005c dret +0+0060 mfdr v1,\$3 +0+0064 mtdr v1,\$3 +0+0068 mfpc a0,1 +0+006c mfps a0,1 +0+0070 mtpc a0,1 +0+0074 mtps a0,1 +0+0078 add\.ob \$f0,\$f1,\$f2 +0+007c add\.ob \$f3,\$f4,\$f6\[2\] +0+0080 add\.ob \$f6,\$f5,0xf +0+0084 add\.ob \$f3,\$f7,0x1f +0+0088 and\.ob \$f0,\$f1,\$f2 +0+008c and\.ob \$f3,\$f4,\$f6\[2\] +0+0090 and\.ob \$f6,\$f5,0xf +0+0094 and\.ob \$f3,\$f7,0x1f +0+0098 c\.eq\.ob \$f0,\$f2 +0+009c c\.eq\.ob \$f3,\$f6\[2\] +0+00a0 c\.eq\.ob \$f6,0xf +0+00a4 c\.eq\.ob \$f3,0x1f +0+00a8 c\.le\.ob \$f0,\$f2 +0+00ac c\.le\.ob \$f3,\$f6\[2\] +0+00b0 c\.le\.ob \$f6,0xf +0+00b4 c\.le\.ob \$f3,0x1f +0+00b8 c\.lt\.ob \$f0,\$f2 +0+00bc c\.lt\.ob \$f3,\$f6\[2\] +0+00c0 c\.lt\.ob \$f6,0xf +0+00c4 c\.lt\.ob \$f3,0x1f +0+00c8 max\.ob \$f0,\$f1,\$f2 +0+00cc max\.ob \$f3,\$f4,\$f6\[2\] +0+00d0 max\.ob \$f6,\$f5,0xf +0+00d4 max\.ob \$f3,\$f7,0x1f +0+00d8 min\.ob \$f0,\$f1,\$f2 +0+00dc min\.ob \$f3,\$f4,\$f6\[2\] +0+00e0 min\.ob \$f6,\$f5,0xf +0+00e4 min\.ob \$f3,\$f7,0x1f +0+00e8 mul\.ob \$f0,\$f1,\$f2 +0+00ec mul\.ob \$f3,\$f4,\$f6\[2\] +0+00f0 mul\.ob \$f6,\$f5,0xf +0+00f4 mul\.ob \$f3,\$f7,0x1f +0+00f8 mula\.ob \$f0,\$f2 +0+00fc mula\.ob \$f3,\$f6\[2\] +0+0100 mula\.ob \$f6,0xf +0+0104 mula\.ob \$f3,0x1f +0+0108 mull\.ob \$f0,\$f2 +0+010c mull\.ob \$f3,\$f6\[2\] +0+0110 mull\.ob \$f6,0xf +0+0114 mull\.ob \$f3,0x1f +0+0118 muls\.ob \$f0,\$f2 +0+011c muls\.ob \$f3,\$f6\[2\] +0+0120 muls\.ob \$f6,0xf +0+0124 muls\.ob \$f3,0x1f +0+0128 mulsl\.ob \$f0,\$f2 +0+012c mulsl\.ob \$f3,\$f6\[2\] +0+0130 mulsl\.ob \$f6,0xf +0+0134 mulsl\.ob \$f3,0x1f +0+0138 nor\.ob \$f0,\$f1,\$f2 +0+013c nor\.ob \$f3,\$f4,\$f6\[2\] +0+0140 nor\.ob \$f6,\$f5,0xf +0+0144 nor\.ob \$f3,\$f7,0x1f +0+0148 or\.ob \$f0,\$f1,\$f2 +0+014c or\.ob \$f3,\$f4,\$f6\[2\] +0+0150 or\.ob \$f6,\$f5,0xf +0+0154 or\.ob \$f3,\$f7,0x1f +0+0158 pickf\.ob \$f0,\$f1,\$f2 +0+015c pickf\.ob \$f3,\$f4,\$f6\[2\] +0+0160 pickf\.ob \$f6,\$f5,0xf +0+0164 pickf\.ob \$f3,\$f7,0x1f +0+0168 pickt\.ob \$f0,\$f1,\$f2 +0+016c pickt\.ob \$f3,\$f4,\$f6\[2\] +0+0170 pickt\.ob \$f6,\$f5,0xf +0+0174 pickt\.ob \$f3,\$f7,0x1f +0+0178 sub\.ob \$f0,\$f1,\$f2 +0+017c sub\.ob \$f3,\$f4,\$f6\[2\] +0+0180 sub\.ob \$f6,\$f5,0xf +0+0184 sub\.ob \$f3,\$f7,0x1f +0+0188 xor\.ob \$f0,\$f1,\$f2 +0+018c xor\.ob \$f3,\$f4,\$f6\[2\] +0+0190 xor\.ob \$f6,\$f5,0xf +0+0194 xor\.ob \$f3,\$f7,0x1f +0+0198 alni\.ob \$f1,\$f2,\$f3,5 +0+019c shfl\.mixh\.ob \$f1,\$f2,\$f3 +0+01a0 shfl\.mixl\.ob \$f1,\$f2,\$f3 +0+01a4 bc2tl 0+4324 +0+01a8 shfl\.pacl\.ob \$f1,\$f2,\$f3 +0+01ac sll\.ob \$f2,\$f4,\$f5\[3\] +0+01b0 sll\.ob \$f3,\$f6,0xe +0+01b4 srl\.ob \$f2,\$f4,\$f5\[3\] +0+01b8 srl\.ob \$f3,\$f6,0xe +0+01bc rzu\.ob \$f2,0xd +0+01c0 rach\.ob \$f2 +0+01c4 racl\.ob \$f2 +0+01c8 bc2f 0+04c8 +0+01cc wach\.ob \$f2 +0+01d0 wacl\.ob \$f2,\$f3 +0+01d4 rorv a0,a1,a2 +0+01d8 ror a0,a1,0x11 +0+01dc drorv a0,a1,a2 +0+01e0 dror32 a0,a1,0x1 +0+01e4 dror a0,a1,0x2 + \.\.\. diff --git a/gas/testsuite/gas/mips/vr5400.s b/gas/testsuite/gas/mips/vr5400.s new file mode 100644 index 00000000000..ae3ad81a930 --- /dev/null +++ b/gas/testsuite/gas/mips/vr5400.s @@ -0,0 +1,125 @@ + .text + +stuff: + .ent stuff + /* Integer instructions. */ + + mul $4,$5,$6 + mulu $4,$5,$6 + mulhi $4,$5,$6 + mulhiu $4,$5,$6 + muls $4,$5,$6 + mulsu $4,$5,$6 + mulshi $4,$5,$6 + mulshiu $4,$5,$6 + macc $4,$5,$6 + maccu $4,$5,$6 + macchi $4,$5,$6 + macchiu $4,$5,$6 + msac $4,$5,$6 + msacu $4,$5,$6 + msachi $4,$5,$6 + msachiu $4,$5,$6 + + ror $4,$5,25 + rorv $4,$5,$6 + dror $4,$5,25 + dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */ + dror32 $4,$5,25 + drorv $4,$5,$6 + + /* Debug instructions. */ + + dbreak + dret + mfdr $3,$3 + mtdr $3,$3 + + /* Coprocessor 0 instructions, minus standard ISA 3 ones. + That leaves just the performance monitoring registers. */ + + mfpc $4,1 + mfps $4,1 + mtpc $4,1 + mtps $4,1 + + /* Multimedia instructions. */ + + .macro nsel2 op + /* Test each form of each vector opcode. */ + \op $f0,$f2 + \op $f3,$f6[2] + \op $f6,15 + .if 0 /* Which is right?? */ + /* Test negative numbers in immediate-value slot. */ + \op $f4,-3 + .else + /* Test that it's recognized as an unsigned field. */ + \op $f3,31 + .endif + .endm + + .macro nsel3 op + /* Test each form of each vector opcode. */ + \op $f0,$f1,$f2 + \op $f3,$f4,$f6[2] + \op $f6,$f5,15 + .if 0 /* Which is right?? */ + /* Test negative numbers in immediate-value slot. */ + \op $f4,$f6,-3 + .else + /* Test that it's recognized as an unsigned field. */ + \op $f3,$f7,31 + .endif + .endm + + nsel3 add.ob + nsel3 and.ob + nsel2 c.eq.ob + nsel2 c.le.ob + nsel2 c.lt.ob + nsel3 max.ob + nsel3 min.ob + nsel3 mul.ob + nsel2 mula.ob + nsel2 mull.ob + nsel2 muls.ob + nsel2 mulsl.ob + nsel3 nor.ob + nsel3 or.ob + nsel3 pickf.ob + nsel3 pickt.ob + nsel3 sub.ob + nsel3 xor.ob + + /* ALNI, SHFL: Vector only. */ + alni.ob $f1,$f2,$f3,5 + shfl.mixh.ob $f1,$f2,$f3 + shfl.mixl.ob $f1,$f2,$f3 + shfl.pach.ob $f1,$f2,$f3 + shfl.pacl.ob $f1,$f2,$f3 + + /* SLL,SRL: Scalar or immediate. */ + sll.ob $f2,$f4,$f5[3] + sll.ob $f3,$f6,14 + srl.ob $f2,$f4,$f5[3] + srl.ob $f3,$f6,14 + + /* RZU: Immediate, must be 0, 8, or 16. */ + rzu.ob $f2,13 + + /* No selector. */ + rach.ob $f2 + racl.ob $f2 + racm.ob $f2 + wach.ob $f2 + wacl.ob $f2,$f3 + + ror $4,$5,$6 + rol $4,$5,15 + dror $4,$5,$6 + drol $4,$5,31 + drol $4,$5,62 + + .space 8 + .end stuff diff --git a/gas/testsuite/gas/mips/vr5500.d b/gas/testsuite/gas/mips/vr5500.d new file mode 100644 index 00000000000..f821ba70f10 --- /dev/null +++ b/gas/testsuite/gas/mips/vr5500.d @@ -0,0 +1,51 @@ +#objdump: -dr --prefix-addresses +#name: MIPS VR5500 +#as: -march=vr5500 + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 mul a0,a1,a2 +0+0004 mulu a0,a1,a2 +0+00008 mulhi a0,a1,a2 +0+0000c mulhiu a0,a1,a2 +0+00010 muls a0,a1,a2 +0+00014 mulsu a0,a1,a2 +0+00018 mulshi a0,a1,a2 +0+0001c mulshiu a0,a1,a2 +0+00020 macc a0,a1,a2 +0+00024 maccu a0,a1,a2 +0+00028 macchi a0,a1,a2 +0+0002c macchiu a0,a1,a2 +0+00030 msac a0,a1,a2 +0+00034 msacu a0,a1,a2 +0+00038 msachi a0,a1,a2 +0+0003c msachiu a0,a1,a2 +0+00040 ror a0,a1,0x19 +0+00044 rorv a0,a1,a2 +0+00048 dror a0,a1,0x19 +0+0004c dror32 a0,a1,0x19 +0+00050 dror32 a0,a1,0x19 +0+00054 drorv a0,a1,a2 +0+00058 prefx 0x4,a0\(a1\) +0+0005c dbreak +0+00060 dret +0+00064 mfdr v1,\$3 +0+00068 mtdr v1,\$3 +0+0006c mfpc a0,1 +0+00070 mfps a0,1 +0+00074 mtpc a0,1 +0+00078 mtps a0,1 +0+0007c wait +0+00080 wait +0+00084 wait 0x56789 +0+00088 ssnop +0+0008c clo v1,a0 +0+00090 dclo v1,a0 +0+00094 clz v1,a0 +0+00098 dclz v1,a0 +0+0009c luxc1 \$f1,a0\(v0\) +0+000a0 suxc1 \$f1,a0\(v0\) +0+000a4 tlbp +0+000a8 tlbr + \.\.\. diff --git a/gas/testsuite/gas/mips/vr5500.s b/gas/testsuite/gas/mips/vr5500.s new file mode 100644 index 00000000000..9d07410b43a --- /dev/null +++ b/gas/testsuite/gas/mips/vr5500.s @@ -0,0 +1,80 @@ + .text + +stuff: + .ent stuff + /* Integer instructions. */ + + mul $4,$5,$6 + mulu $4,$5,$6 + mulhi $4,$5,$6 + mulhiu $4,$5,$6 + muls $4,$5,$6 + mulsu $4,$5,$6 + mulshi $4,$5,$6 + mulshiu $4,$5,$6 + macc $4,$5,$6 + maccu $4,$5,$6 + macchi $4,$5,$6 + macchiu $4,$5,$6 + msac $4,$5,$6 + msacu $4,$5,$6 + msachi $4,$5,$6 + msachiu $4,$5,$6 + + ror $4,$5,25 + rorv $4,$5,$6 + dror $4,$5,25 + dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */ + dror32 $4,$5,25 + drorv $4,$5,$6 + + + /* Prefetch instructions. */ + # We don't test pref because currently the disassembler will + # disassemble it as lwc3. lwc3 is correct for mips1 to mips3, + # while pref is correct for mips4. Unfortunately, the + # disassembler does not know which architecture it is + # disassembling for. + # pref 4,0($4) + + prefx 4,$4($5) + + /* Debug instructions. */ + + dbreak + dret + mfdr $3,$3 + mtdr $3,$3 + + /* Coprocessor 0 instructions, minus standard ISA 3 ones. + That leaves just the performance monitoring registers. */ + + mfpc $4,1 + mfps $4,1 + mtpc $4,1 + mtps $4,1 + + /* Miscellaneous instructions. */ + + wait + wait 0 # disassembles without code + wait 0x56789 + + ssnop + + clo $3,$4 + dclo $3,$4 + clz $3,$4 + dclz $3,$4 + + luxc1 $f1,$4($2) + suxc1 $f1,$4($2) + + tlbp + tlbr + + /* Align to 16-byte boundary. */ + nop + nop + nop + .end stuff