From: lkcl Date: Thu, 24 Dec 2020 09:09:59 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~969 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60bcfdc0d97d0e3941c8d125a0a9e04b1f8c58bb;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 8cbdf53ba..39b1107f6 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -27,7 +27,7 @@ In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both source for i = 0 to VL-1: GPR(RT+i) = GPR(RA+i) + GPR(RB+i) -At its heart, SimpleV really is this simple. On top of this fundamental basis further refinements can be added which build up towards an extremely powerful Vector augmentation system, with very little in the way of additional opcodes required. +At its heart, SimpleV really is this simple. On top of this fundamental basis further refinements can be added which build up towards an extremely powerful Vector augmentation system, with very little in the way of additional opcodes required: simply external "context". RISC-V RVV as of version 0.9 is over 180 instructions (more than the rest of RV64G combined). Over 95% of that functionality is added to OpenPOWER v3 0B, by SimpleV augmentation, with around 5 to 8 instructions.