From: zhengnannan <zhengnannan@huawei.com>
Date: Tue, 3 Nov 2020 13:56:39 +0000 (+0000)
Subject: AArch64: Add FLAG for AES/SHA/SM3/SM4 intrinsics [PR94442]
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60be12c32cb3a07a64efdab1f0ee6fd74536cc93;p=gcc.git

AArch64: Add FLAG for AES/SHA/SM3/SM4 intrinsics [PR94442]

2020-11-03  Zhiheng Xie  <xiezhiheng@huawei.com>
	    Nannan Zheng  <zhengnannan@huawei.com>

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def: Add proper FLAG
	for AES/SHA/SM3/SM4 intrinsics.
---

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 63efdb83cd1..5b78bc536e0 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -514,24 +514,24 @@
   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0, ALL)
 
   /* Implemented by aarch64_crypto_aes<op><mode>.  */
-  VAR1 (BINOPU, crypto_aese, 0, ALL, v16qi)
-  VAR1 (BINOPU, crypto_aesd, 0, ALL, v16qi)
-  VAR1 (UNOPU, crypto_aesmc, 0, ALL, v16qi)
-  VAR1 (UNOPU, crypto_aesimc, 0, ALL, v16qi)
+  VAR1 (BINOPU, crypto_aese, 0, NONE, v16qi)
+  VAR1 (BINOPU, crypto_aesd, 0, NONE, v16qi)
+  VAR1 (UNOPU, crypto_aesmc, 0, NONE, v16qi)
+  VAR1 (UNOPU, crypto_aesimc, 0, NONE, v16qi)
 
   /* Implemented by aarch64_crypto_sha1<op><mode>.  */
-  VAR1 (UNOPU, crypto_sha1h, 0, ALL, si)
-  VAR1 (BINOPU, crypto_sha1su1, 0, ALL, v4si)
-  VAR1 (TERNOPU, crypto_sha1c, 0, ALL, v4si)
-  VAR1 (TERNOPU, crypto_sha1m, 0, ALL, v4si)
-  VAR1 (TERNOPU, crypto_sha1p, 0, ALL, v4si)
-  VAR1 (TERNOPU, crypto_sha1su0, 0, ALL, v4si)
+  VAR1 (UNOPU, crypto_sha1h, 0, NONE, si)
+  VAR1 (BINOPU, crypto_sha1su1, 0, NONE, v4si)
+  VAR1 (TERNOPU, crypto_sha1c, 0, NONE, v4si)
+  VAR1 (TERNOPU, crypto_sha1m, 0, NONE, v4si)
+  VAR1 (TERNOPU, crypto_sha1p, 0, NONE, v4si)
+  VAR1 (TERNOPU, crypto_sha1su0, 0, NONE, v4si)
 
   /* Implemented by aarch64_crypto_sha256<op><mode>.  */
-  VAR1 (TERNOPU, crypto_sha256h, 0, ALL, v4si)
-  VAR1 (TERNOPU, crypto_sha256h2, 0, ALL, v4si)
-  VAR1 (BINOPU, crypto_sha256su0, 0, ALL, v4si)
-  VAR1 (TERNOPU, crypto_sha256su1, 0, ALL, v4si)
+  VAR1 (TERNOPU, crypto_sha256h, 0, NONE, v4si)
+  VAR1 (TERNOPU, crypto_sha256h2, 0, NONE, v4si)
+  VAR1 (BINOPU, crypto_sha256su0, 0, NONE, v4si)
+  VAR1 (TERNOPU, crypto_sha256su1, 0, NONE, v4si)
 
   /* Implemented by aarch64_crypto_pmull<mode>.  */
   VAR1 (BINOPP, crypto_pmull, 0, NONE, di)
@@ -633,27 +633,27 @@
   BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2, FP)
 
   /* Implemented by aarch64_sm3ss1qv4si.  */
-  VAR1 (TERNOPU, sm3ss1q, 0, ALL, v4si)
+  VAR1 (TERNOPU, sm3ss1q, 0, NONE, v4si)
   /* Implemented by aarch64_sm3tt<sm3tt_op>qv4si.  */
-  VAR1 (QUADOPUI, sm3tt1aq, 0, ALL, v4si)
-  VAR1 (QUADOPUI, sm3tt1bq, 0, ALL, v4si)
-  VAR1 (QUADOPUI, sm3tt2aq, 0, ALL, v4si)
-  VAR1 (QUADOPUI, sm3tt2bq, 0, ALL, v4si)
+  VAR1 (QUADOPUI, sm3tt1aq, 0, NONE, v4si)
+  VAR1 (QUADOPUI, sm3tt1bq, 0, NONE, v4si)
+  VAR1 (QUADOPUI, sm3tt2aq, 0, NONE, v4si)
+  VAR1 (QUADOPUI, sm3tt2bq, 0, NONE, v4si)
   /* Implemented by aarch64_sm3partw<sm3part_op>qv4si.  */
-  VAR1 (TERNOPU, sm3partw1q, 0, ALL, v4si)
-  VAR1 (TERNOPU, sm3partw2q, 0, ALL, v4si)
+  VAR1 (TERNOPU, sm3partw1q, 0, NONE, v4si)
+  VAR1 (TERNOPU, sm3partw2q, 0, NONE, v4si)
   /* Implemented by aarch64_sm4eqv4si.  */
-  VAR1 (BINOPU, sm4eq, 0, ALL, v4si)
+  VAR1 (BINOPU, sm4eq, 0, NONE, v4si)
   /* Implemented by aarch64_sm4ekeyqv4si.  */
-  VAR1 (BINOPU, sm4ekeyq, 0, ALL, v4si)
+  VAR1 (BINOPU, sm4ekeyq, 0, NONE, v4si)
   /* Implemented by aarch64_crypto_sha512hqv2di.  */
-  VAR1 (TERNOPU, crypto_sha512hq, 0, ALL, v2di)
+  VAR1 (TERNOPU, crypto_sha512hq, 0, NONE, v2di)
   /* Implemented by aarch64_sha512h2qv2di.  */
-  VAR1 (TERNOPU, crypto_sha512h2q, 0, ALL, v2di)
+  VAR1 (TERNOPU, crypto_sha512h2q, 0, NONE, v2di)
   /* Implemented by aarch64_crypto_sha512su0qv2di.  */
-  VAR1 (BINOPU, crypto_sha512su0q, 0, ALL, v2di)
+  VAR1 (BINOPU, crypto_sha512su0q, 0, NONE, v2di)
   /* Implemented by aarch64_crypto_sha512su1qv2di.  */
-  VAR1 (TERNOPU, crypto_sha512su1q, 0, ALL, v2di)
+  VAR1 (TERNOPU, crypto_sha512su1q, 0, NONE, v2di)
   /* Implemented by eor3q<mode>4.  */
   BUILTIN_VQ_I (TERNOPU, eor3q, 4, ALL)
   BUILTIN_VQ_I (TERNOP, eor3q, 4, ALL)