From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 17 Jul 2020 14:52:39 +0000 (+0200)
Subject: Reduce delay between wishbone_write
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60cbaaeb9dacd2fc0506118b6edc00408e0a7754;p=gram.git

Reduce delay between wishbone_write
---

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 508a35a..e90c19e 100644
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -196,9 +196,9 @@ module simsoctb;
 
       // Write
       wishbone_write(32'h10000000 >> 2, 32'h12345678);
-      #10000;
+      #2000;
       wishbone_write(32'h10000100 >> 2, 32'h00000000);
-      #10000;
+      #2000;
       wishbone_read(32'h10000000 >> 2, tmp);
       assert_equal_32(tmp, 32'h12345678);