From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 6 Aug 2017 15:40:23 +0000 (-0700)
Subject: Moved GP_POR out of digital cells b/c it has delays
X-Git-Tag: yosys-0.8~346^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60dd5dba7ba07b1992123681b37d6ffa6dd2dae4;p=yosys.git

Moved GP_POR out of digital cells b/c it has delays
---

diff --git a/techlibs/greenpak4/cells_sim_ams.v b/techlibs/greenpak4/cells_sim_ams.v
index 370db897d..7f8b3de3b 100644
--- a/techlibs/greenpak4/cells_sim_ams.v
+++ b/techlibs/greenpak4/cells_sim_ams.v
@@ -87,3 +87,24 @@ module GP_VREF(input VIN, output reg VOUT);
 	parameter VREF = 0;
 	//cannot simulate mixed signal IP
 endmodule
+
+module GP_POR(output reg RST_DONE);
+	parameter POR_TIME = 500;
+
+	initial begin
+		RST_DONE = 0;
+
+		if(POR_TIME == 4)
+			#4000;
+		else if(POR_TIME == 500)
+			#500000;
+		else begin
+			$display("ERROR: bad POR_TIME for GP_POR cell");
+			$finish;
+		end
+
+		RST_DONE = 1;
+
+	end
+
+endmodule
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index db5bd9112..f8ab5bf37 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -378,27 +378,6 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 
 endmodule
 
-module GP_POR(output reg RST_DONE);
-	parameter POR_TIME = 500;
-
-	initial begin
-		RST_DONE = 0;
-
-		if(POR_TIME == 4)
-			#4000;
-		else if(POR_TIME == 500)
-			#500000;
-		else begin
-			$display("ERROR: bad POR_TIME for GP_POR cell");
-			$finish;
-		end
-
-		RST_DONE = 1;
-
-	end
-
-endmodule
-
 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 
 	parameter OUTA_TAP = 1;