From: Luke Kenneth Casson Leighton Date: Wed, 5 May 2021 11:46:56 +0000 (+0100) Subject: add sv_input_record_layout to match SVP64RMModeDecode X-Git-Tag: 0.0.3~84 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=60f562d96fa0d09e5f31f9ae3aa959ea2e9e6e9a;p=openpower-isa.git add sv_input_record_layout to match SVP64RMModeDecode --- diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py index 261ed5b9..5f61895e 100644 --- a/src/openpower/decoder/power_svp64_rm.py +++ b/src/openpower/decoder/power_svp64_rm.py @@ -23,6 +23,16 @@ from openpower.consts import EXTRA3, SVP64MODE from openpower.sv.svp64 import SVP64Rec from nmutil.util import sel +# a list of fields which need to be added to input records in order +# pass on vital information needed by each pipeline. +# make sure to keep these the same as SVP64RMModeDecode, in fact, +# TODO, make SVP64RMModeDecode *use* this as a Record! +sv_input_record_layout = [ + ('sv_pred_sz', 1), # predicate source zeroing + ('sv_pred_dz', 1), # predicate dest zeroing + ('sv_saturate', SVP64sat), + #('sv_RC1', 1), + ] """RM Mode there are three Mode variants, two for LD/ST and one for everything else @@ -74,7 +84,7 @@ class SVP64RMModeDecode(Elaboratable): self.dstpred = Signal(3) # destination predicate self.pred_sz = Signal(1) # predicate source zeroing self.pred_dz = Signal(1) # predicate dest zeroing - + self.saturate = Signal(SVP64sat) self.RC1 = Signal() self.cr_sel = Signal(2)