From: Luke Kenneth Casson Leighton Date: Mon, 6 Jul 2020 14:07:36 +0000 (+0100) Subject: add arguments to MulPipe_8_16_32_64 X-Git-Tag: ls180-24jan2020~42 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=610b4a381e70f45f5684cc281398ce77fb5441fa;p=ieee754fpu.git add arguments to MulPipe_8_16_32_64 --- diff --git a/src/ieee754/part_mul_add/mul_pipe.py b/src/ieee754/part_mul_add/mul_pipe.py index c617f2c5..bc3e4e23 100644 --- a/src/ieee754/part_mul_add/mul_pipe.py +++ b/src/ieee754/part_mul_add/mul_pipe.py @@ -52,13 +52,13 @@ class MulPipe_8_16_32_64(ControlBase): """Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier pipeline """ - def __init__(self): + def __init__(self, id_wid=0, op_wid=0): """ register_levels: specifies the points in the cascade at which flip-flops are to be inserted. """ - self.id_wid = 0 # num_bits(num_rows) - self.op_wid = 0 + self.id_wid = id_wid # num_bits(num_rows) + self.op_wid = op_wid self.pspec = PipelineSpec(64, self.id_wid, self.op_wid, n_ops=3) self.pspec.n_parts = 8