From: lkcl <lkcl@web>
Date: Sat, 13 Feb 2021 22:28:03 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~182
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=610ba1a64bd3ee93be82bdf2671801284ff13f70;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 3cced7dd8..71e9925ba 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -135,6 +135,14 @@ Due to the need for exceptions to occur in the middle, the loop should *not* be
 * TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 * Microwatt: TODO
 
+Remember the following register files need to have for-loops, plus
+unit tests:
+
+* GPR
+* SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
+* Condition Registers
+* FPR (if present)
+
 ## Increasing register file sizes
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.