From: Sandipan Das <sandipan@linux.ibm.com>
Date: Sat, 6 Feb 2021 11:52:19 +0000 (+0530)
Subject: arch-power: Fix move condition field instructions
X-Git-Tag: develop-gem5-snapshot~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6116cc7fac289f86e9ca4c101f9d35c142fb360f;p=gem5.git

arch-power: Fix move condition field instructions

This introduces the S field for X form instructions which
is used to specify signed versus unsigned comparison. The
Power ISA does not specify a formal name for the third
1-bit opcode field required for decoding XFX form move to
and from CR field instructions, the S field can be used
to achieve the same as it has the same span and position.
This fixes the following instructions.
  * Move To Condition Register Fields (mtcrf)
  * Move From Condition Register (mfcr)

Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
---

diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa
index 3bfea5306..276242eae 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -73,6 +73,7 @@ def bitfield SPR           <20:11>;
 
 // FXM field for mtcrf instruction
 def bitfield FXM           <19:12>;
+def bitfield S             <20>;
 
 // Branch fields
 def bitfield BO            <25:21>;
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 5f9583436..7f79d3c88 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -972,17 +972,21 @@ decode PO default Unknown::unknown() {
                             0x1f9: mttar({{ TAR = Rs; }});
                         }
 
-                        144: mtcrf({{
-                            uint32_t mask = 0;
-                            for (int i = 0; i < 8; ++i) {
-                                if (((FXM >> i) & 0x1) == 0x1) {
-                                    mask |= 0xf << (4 * i);
+                        144: decode S {
+                            0: mtcrf({{
+                                uint32_t mask = 0;
+                                for (int i = 0; i < 8; ++i) {
+                                    if ((FXM >> i) & 0x1) {
+                                        mask |= 0xf << (4 * i);
+                                    }
                                 }
-                            }
-                            CR = (Rs & mask) | (CR & ~mask);
-                        }});
+                                CR = (Rs & mask) | (CR & ~mask);
+                            }});
+                        }
 
-                        19: mfcr({{ Rt = CR; }});
+                        19: decode S {
+                            0: mfcr({{ Rt = CR; }});
+                        }
 
                         512: mcrxr({{
                             CR = insertCRField(CR, BF, XER<31:28>);