From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 14 Jul 2019 10:03:52 +0000 (-0700)
Subject: finish implementing DivPipeConfig.__init__
X-Git-Tag: ls180-24jan2020~842
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=611c5ee1072afdbb9c140ed0b1bbc8f6dadb4dcf;p=ieee754fpu.git

finish implementing DivPipeConfig.__init__
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 7daac8a9..3fb20315 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -5,20 +5,21 @@
 from .core import (DivPipeCoreConfig, DivPipeCoreInputData,
                    DivPipeCoreInterstageData, DivPipeCoreOutputData)
 from ieee754.fpcommon.getop import FPPipeContext
+from ieee754.fpcommon.fpbase import FPFormat
 
 
 class DivPipeConfig:
     """ Configuration for the div/rem/sqrt/rsqrt pipeline.
 
-    :attribute pspec: FIXME: document
+    :attribute pspec: ``PipelineSpec`` instance
     :attribute core_config: the ``DivPipeCoreConfig`` instance.
     """
 
-    def __init__(self, pspec):
+    def __init__(self, pspec, log2_radix=3):
         """ Create a ``DivPipeConfig`` instance. """
         self.pspec = pspec
-        # FIXME: get bit_width, fract_width, and log2_radix from pspec or pass
-        # in as arguments
+        bit_width = pspec.width
+        fract_width = FPFormat.standard(bit_width).fraction_width
         self.core_config = DivPipeCoreConfig(bit_width,
                                              fract_width,
                                              log2_radix)