From: Nilay Vaish Date: Sat, 19 Mar 2011 23:34:59 +0000 (-0500) Subject: Ruby: Convert CacheRequestType to RubyRequestType X-Git-Tag: stable_2012_02_02~459 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=611f052e963b06b4a7e02b2fc6d847cd6d08d038;p=gem5.git Ruby: Convert CacheRequestType to RubyRequestType This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent code makes use of the same request type. --- diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index ab37a1bd8..705b2831c 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -183,15 +183,15 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -273,7 +273,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index c992e4a68..7923ef65c 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -84,15 +84,15 @@ machine(L1Cache, "MI Example L1 Cache") } // FUNCTIONS - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 310c3027a..291621af9 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -194,15 +194,15 @@ machine(L1Cache, "Directory protocol") } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -309,7 +309,7 @@ machine(L1Cache, "Directory protocol") // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index f801bebd8..8537029e7 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -341,31 +341,31 @@ machine(L1Cache, "Token protocol") } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if (type == CacheRequestType:ST) { + } else if (type == RubyRequestType:ST) { return Event:Store; - } else if (type == CacheRequestType:ATOMIC) { + } else if (type == RubyRequestType:ATOMIC) { if (no_mig_atomic) { return Event:Atomic; } else { return Event:Store; } } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } - AccessType cache_request_type_to_access_type(CacheRequestType type) { - if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) { + AccessType cache_request_type_to_access_type(RubyRequestType type) { + if ((type == RubyRequestType:LD) || (type == RubyRequestType:IFETCH)) { return AccessType:Read; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return AccessType:Write; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -629,7 +629,7 @@ machine(L1Cache, "Token protocol") TBE tbe := L1_TBEs[in_msg.LineAddress]; - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); @@ -1313,7 +1313,7 @@ machine(L1Cache, "Token protocol") peek(mandatoryQueue_in, CacheMsg) { tbe.PC := in_msg.ProgramCounter; tbe.AccessType := cache_request_type_to_access_type(in_msg.Type); - if (in_msg.Type == CacheRequestType:ATOMIC) { + if (in_msg.Type == RubyRequestType:ATOMIC) { tbe.IsAtomic := true; } tbe.Prefetch := in_msg.Prefetch; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 860a7dc1d..ea2a1d6e3 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -214,15 +214,15 @@ machine(L1Cache, "AMD Hammer-like protocol") } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -359,7 +359,7 @@ machine(L1Cache, "AMD Hammer-like protocol") // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache TBE tbe := TBEs[in_msg.LineAddress]; - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); @@ -700,7 +700,7 @@ machine(L1Cache, "AMD Hammer-like protocol") cache_entry.DataBlk); cache_entry.Dirty := true; - if (in_msg.Type == CacheRequestType:ATOMIC) { + if (in_msg.Type == RubyRequestType:ATOMIC) { cache_entry.AtomicAccessed := true; } } diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 7258e9ccd..1f7a1dda2 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -103,16 +103,22 @@ enumeration(TransitionResult, desc="...") { ProtocolStall, desc="Protocol specified stall"; } -// CacheRequestType -enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") { - LD, desc="Load"; - ST, desc="Store"; - ATOMIC, desc="Atomic Load/Store"; - IFETCH, desc="Instruction fetch"; - IO, desc="I/O"; - REPLACEMENT, desc="Replacement"; - COMMIT, desc="Commit version"; - NULL, desc="Invalid request type"; +// RubyRequestType +enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") { + LD, desc="Load"; + ST, desc="Store"; + ATOMIC, desc="Atomic Load/Store"; + IFETCH, desc="Instruction fetch"; + IO, desc="I/O"; + REPLACEMENT, desc="Replacement"; + Load_Linked, desc=""; + Store_Conditional, desc=""; + RMW_Read, desc=""; + RMW_Write, desc=""; + Locked_RMW_Read, desc=""; + Locked_RMW_Write, desc=""; + COMMIT, desc="Commit version"; + NULL, desc="Invalid request type"; } enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") { @@ -211,7 +217,7 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { structure(CacheMsg, desc="...", interface="Message") { Address LineAddress, desc="Line address for this request"; Address PhysicalAddress, desc="Physical address for this request"; - CacheRequestType Type, desc="Type of request (LD, ST, etc)"; + RubyRequestType Type, desc="Type of request (LD, ST, etc)"; Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; RubyAccessMode AccessMode, desc="user/supervisor access type"; int Size, desc="size in bytes of access"; diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.cc b/src/mem/ruby/profiler/AccessTraceForAddress.cc index 9cbf71163..a61c7329f 100644 --- a/src/mem/ruby/profiler/AccessTraceForAddress.cc +++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc @@ -58,17 +58,17 @@ AccessTraceForAddress::print(std::ostream& out) const } void -AccessTraceForAddress::update(CacheRequestType type, +AccessTraceForAddress::update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu, bool sharing_miss) { m_touched_by.add(cpu); m_total++; - if(type == CacheRequestType_ATOMIC) { + if(type == RubyRequestType_ATOMIC) { m_atomics++; - } else if(type == CacheRequestType_LD){ + } else if(type == RubyRequestType_LD){ m_loads++; - } else if (type == CacheRequestType_ST){ + } else if (type == RubyRequestType_ST){ m_stores++; } else { // ERROR_MSG("Trying to add invalid access to trace"); diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh index 9b6db2376..228ebcade 100644 --- a/src/mem/ruby/profiler/AccessTraceForAddress.hh +++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh @@ -32,7 +32,7 @@ #include #include "mem/protocol/RubyAccessMode.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Set.hh" @@ -50,7 +50,7 @@ class AccessTraceForAddress ~AccessTraceForAddress(); void setAddress(const Address& addr) { m_addr = addr; } - void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu, + void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu, bool sharing_miss); int getTotal() const; int getSharing() const { return m_sharing; } diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc index 6ec0e20ba..722845c45 100644 --- a/src/mem/ruby/profiler/AddressProfiler.cc +++ b/src/mem/ruby/profiler/AddressProfiler.cc @@ -257,7 +257,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC, m_getx_sharing_histogram.add(num_indirections); bool indirection_miss = (num_indirections > 0); - addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0), + addTraceSample(datablock, PC, RubyRequestType_ST, RubyAccessMode(0), requestor, indirection_miss); } @@ -274,13 +274,13 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC, m_gets_sharing_histogram.add(num_indirections); bool indirection_miss = (num_indirections > 0); - addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0), + addTraceSample(datablock, PC, RubyRequestType_LD, RubyAccessMode(0), requestor, indirection_miss); } void AddressProfiler::addTraceSample(Address data_addr, Address pc_addr, - CacheRequestType type, + RubyRequestType type, RubyAccessMode access_mode, NodeID id, bool sharing_miss) { diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh index fe822c116..471feaaa5 100644 --- a/src/mem/ruby/profiler/AddressProfiler.hh +++ b/src/mem/ruby/profiler/AddressProfiler.hh @@ -55,7 +55,7 @@ class AddressProfiler void clearStats(); void addTraceSample(Address data_addr, Address pc_addr, - CacheRequestType type, RubyAccessMode access_mode, + RubyRequestType type, RubyAccessMode access_mode, NodeID id, bool sharing_miss); void profileRetry(const Address& data_addr, AccessType type, int count); void profileGetX(const Address& datablock, const Address& PC, diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc index fcad227fb..fdb4581bb 100644 --- a/src/mem/ruby/profiler/CacheProfiler.cc +++ b/src/mem/ruby/profiler/CacheProfiler.cc @@ -33,7 +33,7 @@ using namespace std; CacheProfiler::CacheProfiler(const string& description) - : m_cacheRequestType(int(CacheRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM)) + : m_cacheRequestType(int(RubyRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM)) { m_description = description; @@ -59,7 +59,7 @@ CacheProfiler::printStats(ostream& out) const int requests = 0; - for (int i = 0; i < int(CacheRequestType_NUM); i++) { + for (int i = 0; i < int(RubyRequestType_NUM); i++) { requests += m_cacheRequestType[i]; } @@ -70,10 +70,10 @@ CacheProfiler::printStats(ostream& out) const assert(m_misses == requests); if (requests > 0) { - for (int i = 0; i < int(CacheRequestType_NUM); i++) { + for (int i = 0; i < int(RubyRequestType_NUM); i++) { if (m_cacheRequestType[i] > 0) { out << description << "_request_type_" - << CacheRequestType_to_string(CacheRequestType(i)) + << RubyRequestType_to_string(RubyRequestType(i)) << ": " << 100.0 * (double)m_cacheRequestType[i] / (double)requests @@ -111,7 +111,7 @@ CacheProfiler::printStats(ostream& out) const void CacheProfiler::clearStats() { - for (int i = 0; i < int(CacheRequestType_NUM); i++) { + for (int i = 0; i < int(RubyRequestType_NUM); i++) { m_cacheRequestType[i] = 0; } for (int i = 0; i < int(GenericRequestType_NUM); i++) { @@ -128,7 +128,7 @@ CacheProfiler::clearStats() } void -CacheProfiler::addCacheStatSample(CacheRequestType requestType, +CacheProfiler::addCacheStatSample(RubyRequestType requestType, RubyAccessMode accessType, PrefetchBit pfBit) { diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh index 9a8fdefb4..1ae6ba7a8 100644 --- a/src/mem/ruby/profiler/CacheProfiler.hh +++ b/src/mem/ruby/profiler/CacheProfiler.hh @@ -34,7 +34,7 @@ #include #include "mem/protocol/RubyAccessMode.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/ruby/common/Global.hh" @@ -50,7 +50,7 @@ class CacheProfiler void printStats(std::ostream& out) const; void clearStats(); - void addCacheStatSample(CacheRequestType requestType, + void addCacheStatSample(RubyRequestType requestType, RubyAccessMode type, PrefetchBit pfBit); diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc index 8596d04f1..8604d014f 100644 --- a/src/mem/ruby/profiler/Profiler.cc +++ b/src/mem/ruby/profiler/Profiler.cc @@ -320,7 +320,7 @@ Profiler::printStats(ostream& out, bool short_stats) out << "prefetch_latency: " << m_allSWPrefetchLatencyHistogram << endl; for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) { if (m_SWPrefetchLatencyHistograms[i].size() > 0) { - out << "prefetch_latency_" << CacheRequestType(i) << ": " + out << "prefetch_latency_" << RubyRequestType(i) << ": " << m_SWPrefetchLatencyHistograms[i] << endl; } } @@ -500,7 +500,7 @@ Profiler::clearStats() m_dirFirstResponseToCompleteHistogram.clear(200); m_dirIncompleteTimes = 0; - m_SWPrefetchLatencyHistograms.resize(CacheRequestType_NUM); + m_SWPrefetchLatencyHistograms.resize(RubyRequestType_NUM); for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) { m_SWPrefetchLatencyHistograms[i].clear(200); } @@ -537,7 +537,7 @@ Profiler::clearStats() void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id) { - if (msg.getType() != CacheRequestType_IFETCH) { + if (msg.getType() != RubyRequestType_IFETCH) { // Note: The following line should be commented out if you // want to use the special profiling that is part of the GS320 // protocol @@ -683,7 +683,7 @@ Profiler::missLatencyDir(Time issuedTime, // non-zero cycle prefetch request void Profiler::swPrefetchLatency(Time cycles, - CacheRequestType type, + RubyRequestType type, const GenericMachineType respondingMach) { m_allSWPrefetchLatencyHistogram.add(cycles); diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index a3eb8cd71..8e3e7f547 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -53,7 +53,7 @@ #include "base/hashmap.hh" #include "mem/protocol/RubyAccessMode.hh" #include "mem/protocol/AccessType.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/GenericMachineType.hh" #include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/PrefetchBit.hh" @@ -150,7 +150,7 @@ class Profiler : public SimObject, public Consumer Time completionTime); void swPrefetchLatency(Time t, - CacheRequestType type, + RubyRequestType type, const GenericMachineType respondingMach); void sequencerRequests(int num) { m_sequencer_requests.add(num); } diff --git a/src/mem/ruby/recorder/CacheRecorder.hh b/src/mem/ruby/recorder/CacheRecorder.hh index 08a38695c..1aac9a7e2 100644 --- a/src/mem/ruby/recorder/CacheRecorder.hh +++ b/src/mem/ruby/recorder/CacheRecorder.hh @@ -38,7 +38,7 @@ #include #include -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/system/NodeID.hh" #include "mem/ruby/recorder/TraceRecord.hh" diff --git a/src/mem/ruby/recorder/Tracer.hh b/src/mem/ruby/recorder/Tracer.hh index 2de4ef164..39bab72a1 100644 --- a/src/mem/ruby/recorder/Tracer.hh +++ b/src/mem/ruby/recorder/Tracer.hh @@ -39,7 +39,7 @@ #include "gzstream.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/system/NodeID.hh" #include "params/RubyTracer.hh" diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc index 9189bfa7a..2d8c94ed6 100644 --- a/src/mem/ruby/slicc_interface/RubyRequest.cc +++ b/src/mem/ruby/slicc_interface/RubyRequest.cc @@ -4,69 +4,6 @@ using namespace std; -string -RubyRequestType_to_string(const RubyRequestType& obj) -{ - switch(obj) { - case RubyRequestType_IFETCH: - return "IFETCH"; - case RubyRequestType_LD: - return "LD"; - case RubyRequestType_ST: - return "ST"; - case RubyRequestType_Load_Linked: - return "Load_Linked"; - case RubyRequestType_Store_Conditional: - return "Store_Conditional"; - case RubyRequestType_RMW_Read: - return "RMW_Read"; - case RubyRequestType_RMW_Write: - return "RMW_Write"; - case RubyRequestType_Locked_RMW_Read: - return "Locked_RMW_Read"; - case RubyRequestType_Locked_RMW_Write: - return "Locked_RMW_Write"; - case RubyRequestType_NULL: - default: - assert(0); - return ""; - } -} - -RubyRequestType -string_to_RubyRequestType(string str) -{ - if (str == "IFETCH") - return RubyRequestType_IFETCH; - else if (str == "LD") - return RubyRequestType_LD; - else if (str == "ST") - return RubyRequestType_ST; - else if (str == "Locked_Read") - return RubyRequestType_Load_Linked; - else if (str == "Locked_Write") - return RubyRequestType_Store_Conditional; - else if (str == "RMW_Read") - return RubyRequestType_RMW_Read; - else if (str == "RMW_Write") - return RubyRequestType_RMW_Write; - else if (str == "Locked_RMW_Read") - return RubyRequestType_Locked_RMW_Read; - else if (str == "Locked_RMW_Write") - return RubyRequestType_Locked_RMW_Write; - else - assert(0); - return RubyRequestType_NULL; -} - -ostream& -operator<<(ostream& out, const RubyRequestType& obj) -{ - out << RubyRequestType_to_string(obj); - out << flush; - return out; -} - ostream& operator<<(ostream& out, const RubyRequest& obj) { diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh index 6d0e23bfe..d7acfd578 100644 --- a/src/mem/ruby/slicc_interface/RubyRequest.hh +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh @@ -33,25 +33,12 @@ #include "mem/packet.hh" #include "mem/protocol/RubyAccessMode.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/Message.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/ruby/common/Address.hh" typedef void* RubyPortHandle; -enum RubyRequestType { - RubyRequestType_NULL, - RubyRequestType_IFETCH, - RubyRequestType_LD, - RubyRequestType_ST, - RubyRequestType_Load_Linked, - RubyRequestType_Store_Conditional, - RubyRequestType_RMW_Read, - RubyRequestType_RMW_Write, - RubyRequestType_Locked_RMW_Read, - RubyRequestType_Locked_RMW_Write, - RubyRequestType_NUM -}; class RubyRequest { @@ -87,9 +74,6 @@ class RubyRequest void print(std::ostream& out) const; }; -std::string RubyRequestType_to_string(const RubyRequestType& obj); -RubyRequestType string_to_RubyRequestType(std::string); -std::ostream& operator<<(std::ostream& out, const RubyRequestType& obj); std::ostream& operator<<(std::ostream& out, const RubyRequest& obj); #endif diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh index 81de8e468..bb23406b9 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -37,7 +37,7 @@ #include "mem/protocol/AccessType.hh" #include "mem/protocol/CacheMsg.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/Directory_State.hh" #include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/L1Cache_State.hh" diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 7fcb5431b..ea5054e4c 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -159,7 +159,7 @@ CacheMemory::findTagInSetIgnorePermissions(Index cacheSet, } bool -CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type, +CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr) { assert(address == line_address(address)); @@ -177,7 +177,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type, return true; } if ((entry->m_Permission == AccessPermission_Read_Only) && - (type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) { + (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) { return true; } // The line must not be accessible @@ -187,7 +187,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type, } bool -CacheMemory::testCacheAccess(const Address& address, CacheRequestType type, +CacheMemory::testCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr) { assert(address == line_address(address)); @@ -367,18 +367,18 @@ CacheMemory::recordCacheContents(CacheRecorder& tr) const for (int i = 0; i < m_cache_num_sets; i++) { for (int j = 0; j < m_cache_assoc; j++) { AccessPermission perm = m_cache[i][j]->m_Permission; - CacheRequestType request_type = CacheRequestType_NULL; + RubyRequestType request_type = RubyRequestType_NULL; if (perm == AccessPermission_Read_Only) { if (m_is_instruction_only_cache) { - request_type = CacheRequestType_IFETCH; + request_type = RubyRequestType_IFETCH; } else { - request_type = CacheRequestType_LD; + request_type = RubyRequestType_LD; } } else if (perm == AccessPermission_Read_Write) { - request_type = CacheRequestType_ST; + request_type = RubyRequestType_ST; } - if (request_type != CacheRequestType_NULL) { + if (request_type != RubyRequestType_NULL) { #if 0 tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address, Address(0), request_type, diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index 6e311edc3..4e7acd4ec 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -36,7 +36,7 @@ #include "base/hashmap.hh" #include "mem/protocol/AccessPermission.hh" #include "mem/protocol/CacheMsg.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/MachineType.hh" #include "mem/ruby/common/Address.hh" @@ -66,11 +66,11 @@ class CacheMemory : public SimObject void printConfig(std::ostream& out); // perform a cache access and see if we hit or not. Return true on a hit. - bool tryCacheAccess(const Address& address, CacheRequestType type, + bool tryCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr); // similar to above, but doesn't require full access check - bool testCacheAccess(const Address& address, CacheRequestType type, + bool testCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr); // tests to see if an address is present in the cache diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index e8e279043..772bc5142 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -64,15 +64,7 @@ DMASequencer::makeRequest(const RubyRequest &request) case RubyRequestType_ST: write = true; break; - case RubyRequestType_NULL: - case RubyRequestType_IFETCH: - case RubyRequestType_Load_Linked: - case RubyRequestType_Store_Conditional: - case RubyRequestType_RMW_Read: - case RubyRequestType_RMW_Write: - case RubyRequestType_Locked_RMW_Read: - case RubyRequestType_Locked_RMW_Write: - case RubyRequestType_NUM: + default: panic("DMASequencer::makeRequest does not support RubyRequestType"); return RequestStatus_NULL; } diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 7f916957b..6b0f6e49f 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -604,16 +604,16 @@ Sequencer::makeRequest(const RubyRequest &request) void Sequencer::issueRequest(const RubyRequest& request) { - // TODO: get rid of CacheMsg, CacheRequestType, and + // TODO: get rid of CacheMsg, RubyRequestType, and // AccessModeTYpe, & have SLICC use RubyRequest and subtypes // natively - CacheRequestType ctype; + RubyRequestType ctype; switch(request.type) { case RubyRequestType_IFETCH: - ctype = CacheRequestType_IFETCH; + ctype = RubyRequestType_IFETCH; break; case RubyRequestType_LD: - ctype = CacheRequestType_LD; + ctype = RubyRequestType_LD; break; case RubyRequestType_ST: case RubyRequestType_RMW_Read: @@ -626,7 +626,7 @@ Sequencer::issueRequest(const RubyRequest& request) // case RubyRequestType_Locked_RMW_Read: case RubyRequestType_Locked_RMW_Write: - ctype = CacheRequestType_ST; + ctype = RubyRequestType_ST; break; // // Alpha LL/SC instructions need to be handled carefully by the cache @@ -638,7 +638,7 @@ Sequencer::issueRequest(const RubyRequest& request) // case RubyRequestType_Load_Linked: case RubyRequestType_Store_Conditional: - ctype = CacheRequestType_ATOMIC; + ctype = RubyRequestType_ATOMIC; break; default: assert(0); @@ -685,12 +685,12 @@ Sequencer::issueRequest(const RubyRequest& request) #if 0 bool -Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type, +Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type, RubyAccessMode access_mode, int size, DataBlock*& data_ptr) { CacheMemory *cache = - (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr; + (type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr; return cache->tryCacheAccess(line_address(addr), type, data_ptr); } diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 7793af889..14b6997e8 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -33,7 +33,7 @@ #include "base/hashmap.hh" #include "mem/protocol/RubyAccessMode.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/GenericMachineType.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/ruby/common/Address.hh" @@ -112,7 +112,7 @@ class Sequencer : public RubyPort, public Consumer void removeRequest(SequencerRequest* request); private: - bool tryCacheAccess(const Address& addr, CacheRequestType type, + bool tryCacheAccess(const Address& addr, RubyRequestType type, const Address& pc, RubyAccessMode access_mode, int size, DataBlock*& data_ptr); void issueRequest(const RubyRequest& request);