From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Dec 2017 01:29:19 +0000 (+0100)
Subject: Fix a bug in clk2fflogic memory handling
X-Git-Tag: yosys-0.8~248
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6132e6e72a95a6f57e209bfa801c4ac5c1faa974;p=yosys.git

Fix a bug in clk2fflogic memory handling
---

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index d334cf7d9..7e952e99b 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -126,7 +126,7 @@ struct Clk2fflogicPass : public Pass {
 
 						SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
 
-						SigSpec en_q = module->addWire(NEW_ID, GetSize(addr));
+						SigSpec en_q = module->addWire(NEW_ID, GetSize(en));
 						module->addFf(NEW_ID, en, en_q);
 
 						SigSpec addr_q = module->addWire(NEW_ID, GetSize(addr));