From: Cole Poirier <colepoirier@gmail.com>
Date: Wed, 26 Aug 2020 18:06:12 +0000 (-0700)
Subject: Merge branch 'master' of git.libre-soc.org:soc
X-Git-Tag: semi_working_ecp5~252
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61440c972436f418a0c115ac75153bce2bc50cb3;hp=5f4f10a064161cbda3437ffb2b49710df03a82d8;p=soc.git

Merge branch 'master' of git.libre-soc.org:soc
---

diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 700a6206..f98f6162 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -254,7 +254,9 @@ class SelectableInt:
         return SelectableInt(~self.value, self.bits)
 
     def __neg__(self):
-        return SelectableInt(~self.value + 1, self.bits)
+        res = SelectableInt((~self.value) + 1, self.bits)
+        print ("neg", hex(self.value), hex(res.value))
+        return res
 
     def __lshift__(self, b):
         b = check_extsign(self, b)
diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 9a978b45..c4280fee 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -226,7 +226,7 @@ class AllFunctionUnits(Elaboratable):
 
     """
 
-    def __init__(self, pspec, pilist=None, div_fsm=False):
+    def __init__(self, pspec, pilist=None, div_fsm=True):
         addrwid = pspec.addr_wid
         units = pspec.units
         if not isinstance(units, dict):
diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index ee8e5b95..4c8ee387 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -12,7 +12,7 @@ from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
 
 class DivTestCases(TestAccumulatorBase):
     def case_divw_regression(self):
-        # simulator is wrong, FSM and power-instruction-analyzer are both correct
+        # simulator is wrong, FSM and power-instruction-analyzer both correct
         lst = [f"divw 0, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[2] = 0x2
diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 298f359c..8af95ead 100644
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -158,6 +158,50 @@ class TestRunner(FHDLTestCase):
         super().__init__("run_all")
         self.test_data = test_data
 
+    def execute(self, alu,instruction, pdecode2, test):
+        print(test.name)
+        program = test.program
+        self.subTest(test.name)
+        simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                        test.mem, test.msr,
+                        bigendian=bigendian)
+        gen = program.generate_instructions()
+        instructions = list(zip(gen, program.assembly.splitlines()))
+
+        index = simulator.pc.CIA.value//4
+        while index < len(instructions):
+            ins, code = instructions[index]
+
+            print("0x{:X}".format(ins & 0xffffffff))
+            print(code)
+
+            # ask the decoder to decode this binary data (endian'd)
+            yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
+            yield instruction.eq(ins)          # raw binary instr.
+            yield Settle()
+            fn_unit = yield pdecode2.e.do.fn_unit
+            self.assertEqual(fn_unit, Function.LOGICAL.value, code)
+            yield from set_alu_inputs(alu, pdecode2, simulator)
+
+            # set valid for one cycle, propagate through pipeline...
+            yield alu.p.valid_i.eq(1)
+            yield
+            yield alu.p.valid_i.eq(0)
+
+            opname = code.split(' ')[0]
+            yield from simulator.call(opname)
+            index = simulator.pc.CIA.value//4
+
+            vld = yield alu.n.valid_o
+            while not vld:
+                yield
+                vld = yield alu.n.valid_o
+            yield
+
+            yield from self.check_alu_outputs(alu, pdecode2,
+                                              simulator, code)
+            yield Settle()
+
     def run_all(self):
         m = Module()
         comb = m.d.comb
@@ -181,47 +225,8 @@ class TestRunner(FHDLTestCase):
             for test in self.test_data:
                 print(test.name)
                 program = test.program
-                self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr,
-                                bigendian=bigendian)
-                gen = program.generate_instructions()
-                instructions = list(zip(gen, program.assembly.splitlines()))
-
-                index = simulator.pc.CIA.value//4
-                while index < len(instructions):
-                    ins, code = instructions[index]
-
-                    print("0x{:X}".format(ins & 0xffffffff))
-                    print(code)
-
-                    # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
-                    yield instruction.eq(ins)          # raw binary instr.
-                    yield Settle()
-                    fn_unit = yield pdecode2.e.do.fn_unit
-                    self.assertEqual(fn_unit, Function.LOGICAL.value, code)
-                    yield from set_alu_inputs(alu, pdecode2, simulator)
-
-                    # set valid for one cycle, propagate through pipeline...
-                    yield alu.p.valid_i.eq(1)
-                    yield
-                    yield alu.p.valid_i.eq(0)
-
-                    opname = code.split(' ')[0]
-                    yield from simulator.call(opname)
-                    index = simulator.pc.CIA.value//4
-
-                    vld = yield alu.n.valid_o
-                    while not vld:
-                        yield
-                        vld = yield alu.n.valid_o
-                    yield
-
-                    yield from self.check_alu_outputs(alu, pdecode2,
-                                                      simulator, code)
-                    yield Settle()
-
+                with self.subTest(test.name):
+                    yield from self.execute(alu, instruction, pdecode2, test)
 
         sim.add_sync_process(process)
         with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",