From: Georg-Johann Lay Date: Mon, 2 Oct 2017 11:31:03 +0000 (+0000) Subject: re PR target/41076 ([avr] pessimal code for logical OR of 8-bit fields) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6146ee73730cd2a4406918a0d5f98f0f71331f01;p=gcc.git re PR target/41076 ([avr] pessimal code for logical OR of 8-bit fields) PR target/41076 * confg/avr/avr.md (*iorhi3.ashift8-ext.zerox): Add "r,r,0" alternative. From-SVN: r253343 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a2e33e4b910..8abda0a7bdb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-10-02 Georg-Johann Lay + + PR target/41076 + * confg/avr/avr.md (*iorhi3.ashift8-ext.zerox): Add "r,r,0" + alternative. + 2017-10-02 Richard Biener * graphite-isl-ast-to-gimple.c (set_codegen_error): With diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index fe5ca303ef7..436f036704a 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -6804,11 +6804,11 @@ (define_insn_and_split "*iorhi3.ashift8-ext.zerox" - [(set (match_operand:HI 0 "register_operand" "=r") + [(set (match_operand:HI 0 "register_operand" "=r,r") (ior:HI (ashift:HI (any_extend:HI - (match_operand:QI 1 "register_operand" "r")) + (match_operand:QI 1 "register_operand" "r,r")) (const_int 8)) - (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))] + (zero_extend:HI (match_operand:QI 2 "register_operand" "0,r"))))] "optimize" { gcc_unreachable(); } "&& reload_completed"