From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Tue, 9 Jun 2020 07:53:00 +0000 (+0200)
Subject: Fix input/output attributes when resolving typedef of wire
X-Git-Tag: working-ls180~123^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61501e3266238f6c4cffafb08ed85ff86f912cf4;p=yosys.git

Fix input/output attributes when resolving typedef of wire

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index d4242f1e7..fc2976c83 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1330,6 +1330,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) {
 				// replace with wire representing the packed structure
 				newNode = make_packed_struct(template_node, str);
+				// add original input/output attribute to resolved wire
+				newNode->is_input = this->is_input;
+				newNode->is_output = this->is_output;
 				current_scope[str] = this;
 				goto apply_newNode;
 			}