From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Wed, 1 May 2019 14:10:44 +0000 (+0200)
Subject: radv: do not need to force emit the TCS regs on Vega20
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61625439999e3658dddf58485fc0ef85ecf082fc;p=mesa.git

radv: do not need to force emit the TCS regs on Vega20

This chip doesn't need the fixup. This fixes a bunch of
dEQP-VK.tessellation tests and avoid random GPU hangs.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index adf158e30e1..b4a19aa2e5d 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3691,6 +3691,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
 		ac_init_exec_full_mask(&ctx.ac);
 
 	if (ctx.ac.chip_class == GFX9 &&
+	    ctx.ac.family != CHIP_VEGA20 &&
 	    shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
 		ac_nir_fixup_ls_hs_input_vgprs(&ctx);