From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Jul 2020 23:22:00 +0000 (+0100)
Subject: allow flexible selection of the types of ALUs
X-Git-Tag: div_pipeline~165
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=616e488006addc1e2a804ed53155e8b2100729ae;p=soc.git

allow flexible selection of the types of ALUs
---

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index bec55b83..6de63d05 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -178,17 +178,23 @@ class AllFunctionUnits(Elaboratable):
      * type of FU required
 
     """
-    def __init__(self, pspec, pilist=None, addrwid=6):
+    def __init__(self, pspec, pilist=None):
+        addrwid = pspec.addr_wid
+        units = pspec.units
+        if not isinstance(units, dict):
+            units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
+                     'div': 1, 'shiftrot': 1}
+        alus = {'alu': ALUFunctionUnit,
+                 'cr': CRFunctionUnit,
+                 'branch': BranchFunctionUnit,
+                 'trap': TrapFunctionUnit,
+                 'div': DIVFunctionUnit,
+                 'logical': LogicalFunctionUnit,
+                 'shiftrot': ShiftRotFunctionUnit,
+                }
         self.fus = {}
-        for (name, qty, kls) in (('alu', 1, ALUFunctionUnit),
-                                 ('cr', 1, CRFunctionUnit),
-                                 ('branch', 1, BranchFunctionUnit),
-                                 ('trap', 1, TrapFunctionUnit),
-                                 # far too large at the moment
-                                 #('div', 1, DIVFunctionUnit),
-                                 ('logical', 1, LogicalFunctionUnit),
-                                 ('shiftrot', 1, ShiftRotFunctionUnit),
-                                ):
+        for name, qty in units.items():
+            kls = alus[name]
             for i in range(qty):
                 self.fus["%s%d" % (name, i)] = kls(i)
         if pilist is None:
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index a158e199..8e4ff93f 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -55,13 +55,12 @@ def sort_fuspecs(fuspecs):
 
 class NonProductionCore(Elaboratable):
     def __init__(self, pspec):
-        addrwid = pspec.addr_wid
         # single LD/ST funnel for memory access
         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
         pi = self.l0.l0.dports[0]
 
         # function units (only one each)
-        self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)
+        self.fus = AllFunctionUnits(pspec, pilist=[pi])
 
         # register files (yes plural)
         self.regs = RegFiles()
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index a610f60d..0ba74997 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -161,11 +161,14 @@ class TestIssuer(Elaboratable):
 
 
 if __name__ == '__main__':
+    units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
+             'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
                          mask_wid=8,
-                         reg_wid=64)
+                         reg_wid=64,
+                         units=units)
     dut = TestIssuer(pspec)
     vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
     with open("test_issuer.il", "w") as f: