From: Segher Boessenkool Date: Wed, 17 Apr 2019 09:45:57 +0000 (+0200) Subject: rs6000: Improve the load/store-with-update patterns (PR17108) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61943f94a0acfe2f61ed9c320a45a654d6baa780;p=gcc.git rs6000: Improve the load/store-with-update patterns (PR17108) Many of these patterns only worked in 32-bit mode, and some only worked in 64-bit mode. This patch makes these use Pmode, fixing the PR. On the other hand, the stack updates have to use the same mode for the stack pointer as for the value stored, so let's simplify that a bit. Many of these patterns pass the wrong mode to avoiding_indexed_address_p (it should be the mode of the datum accessed, not the mode of the pointer). Finally, I merge some patterns into one (using iterators). PR target/17108 * config/rs6000/rs6000.c (rs6000_split_multireg_move): Adjust pattern name. (rs6000_emit_allocate_stack_1): Simplify condition. Adjust pattern name. * config/rs6000/rs6000.md (bits): Add entries for SF and DF. (*movdi_update1): Use Pmode. (movdi__update): Fix argument to avoiding_indexed_address_p. (movdi__update_stack): Rename to ... (movdi_update_stack): ... this. Fix comment. Change condition. Don't use Pmode. (*movsi_update1): Use Pmode. (*movsi_update2): Use Pmode. (movsi_update): Rename to ... (movsi__update): ... this. Use Pmode. (movsi_update_stack): Fix condition. (*movhi_update1): Use Pmode. Fix argument to avoiding_indexed_address_p. (*movhi_update2): Ditto. (*movhi_update3): Ditto. (*movhi_update4): Ditto. (*movqi_update1): Ditto. (*movqi_update2): Ditto. (*movqi_update3): Ditto. (*movsf_update1, *movdf_update1): Merge, rename to... (*mov_update1): This. Use Pmode. Fix argument to avoiding_indexed_address_p. Add "size" attribute. (*movsf_update2, *movdf_update2): Merge, rename to... (*mov_update2): This. Ditto. (*movsf_update3): Use Pmode. Fix argument to avoiding_indexed_address_p. (*movsf_update4): Ditto. (allocate_stack): Simplify condition. Adjust pattern names. From-SVN: r270407 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 231bb83c4f3..9480e693c08 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,39 @@ +2019-04-17 Segher Boessenkool + + PR target/17108 + * config/rs6000/rs6000.c (rs6000_split_multireg_move): Adjust pattern + name. + (rs6000_emit_allocate_stack_1): Simplify condition. Adjust pattern + name. + * config/rs6000/rs6000.md (bits): Add entries for SF and DF. + (*movdi_update1): Use Pmode. + (movdi__update): Fix argument to avoiding_indexed_address_p. + (movdi__update_stack): Rename to ... + (movdi_update_stack): ... this. Fix comment. Change condition. Don't + use Pmode. + (*movsi_update1): Use Pmode. + (*movsi_update2): Use Pmode. + (movsi_update): Rename to ... + (movsi__update): ... this. Use Pmode. + (movsi_update_stack): Fix condition. + (*movhi_update1): Use Pmode. Fix argument to + avoiding_indexed_address_p. + (*movhi_update2): Ditto. + (*movhi_update3): Ditto. + (*movhi_update4): Ditto. + (*movqi_update1): Ditto. + (*movqi_update2): Ditto. + (*movqi_update3): Ditto. + (*movsf_update1, *movdf_update1): Merge, rename to... + (*mov_update1): This. Use Pmode. Fix argument to + avoiding_indexed_address_p. Add "size" attribute. + (*movsf_update2, *movdf_update2): Merge, rename to... + (*mov_update2): This. Ditto. + (*movsf_update3): Use Pmode. Fix argument to + avoiding_indexed_address_p. + (*movsf_update4): Ditto. + (allocate_stack): Simplify condition. Adjust pattern names. + 2019-04-17 Jakub Jelinek PR target/89093 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9105253d763..ae2249b7d5a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -24010,7 +24010,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) emit_insn (TARGET_32BIT ? (TARGET_POWERPC64 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) - : gen_movsi_update (breg, breg, delta_rtx, nsrc)) + : gen_movsi_si_update (breg, breg, delta_rtx, nsrc)) : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); used_update = true; } @@ -25486,16 +25486,16 @@ rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp) size_rtx = tmp_reg; } - if (Pmode == SImode) + if (TARGET_32BIT) insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx, stack_pointer_rtx, size_rtx, orig_sp)); else - insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx, - stack_pointer_rtx, - size_rtx, - orig_sp)); + insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx, + stack_pointer_rtx, + size_rtx, + orig_sp)); rtx par = PATTERN (insn); gcc_assert (GET_CODE (par) == PARALLEL); rtx set = XVECEXP (par, 0, 0); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b8dd85905f3..6feaa10c155 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -563,7 +563,8 @@ (TI "q")]) ;; How many bits in this mode? -(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")]) +(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64") + (SF "32") (DF "64")]) ; DImode bits (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) @@ -9083,13 +9084,13 @@ (define_insn "*movdi_update1" [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") - (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") - (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) - (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") - (plus:DI (match_dup 1) (match_dup 2)))] + (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64 && TARGET_UPDATE && (!avoiding_indexed_address_p (DImode) - || !gpc_reg_operand (operands[2], DImode))" + || !gpc_reg_operand (operands[2], Pmode))" "@ ldux %3,%0,%2 ldu %3,%2(%0)" @@ -9099,12 +9100,12 @@ (define_insn "movdi__update" [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") - (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) + (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) (match_operand:DI 3 "gpc_reg_operand" "r,r")) (set (match_operand:P 0 "gpc_reg_operand" "=b,b") (plus:P (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64 && TARGET_UPDATE - && (!avoiding_indexed_address_p (Pmode) + && (!avoiding_indexed_address_p (DImode) || !gpc_reg_operand (operands[2], Pmode) || (REG_P (operands[0]) && REGNO (operands[0]) == STACK_POINTER_REGNUM))" @@ -9115,15 +9116,15 @@ (set_attr "update" "yes") (set_attr "indexed" "yes,no")]) -;; This pattern is only conditional on TARGET_POWERPC64, as it is +;; This pattern is only conditional on TARGET_64BIT, as it is ;; needed for stack allocation, even if the user passes -mno-update. -(define_insn "movdi__update_stack" - [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") - (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) +(define_insn "movdi_update_stack" + [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") + (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) (match_operand:DI 3 "gpc_reg_operand" "r,r")) - (set (match_operand:P 0 "gpc_reg_operand" "=b,b") - (plus:P (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64" + (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") + (plus:DI (match_dup 1) (match_dup 2)))] + "TARGET_64BIT" "@ stdux %3,%0,%2 stdu %3,%2(%0)" @@ -9133,13 +9134,13 @@ (define_insn "*movsi_update1" [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") - (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (mem:SI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I")))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + || !gpc_reg_operand (operands[2], Pmode))" "@ lwzux %3,%0,%2 lwzu %3,%2(%0)" @@ -9148,12 +9149,12 @@ (set_attr "indexed" "yes,no")]) (define_insn "*movsi_update2" - [(set (match_operand:DI 3 "gpc_reg_operand" "=r") - (sign_extend:DI - (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") - (match_operand:DI 2 "gpc_reg_operand" "r"))))) - (set (match_operand:DI 0 "gpc_reg_operand" "=b") - (plus:DI (match_dup 1) (match_dup 2)))] + [(set (match_operand:EXTSI 3 "gpc_reg_operand" "=r") + (sign_extend:EXTSI + (mem:SI (plus:P (match_operand:P 1 "gpc_reg_operand" "0") + (match_operand:P 2 "gpc_reg_operand" "r"))))) + (set (match_operand:P 0 "gpc_reg_operand" "=b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64 && !avoiding_indexed_address_p (DImode)" "lwaux %3,%0,%2" [(set_attr "type" "load") @@ -9161,15 +9162,15 @@ (set_attr "update" "yes") (set_attr "indexed" "yes")]) -(define_insn "movsi_update" - [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))) +(define_insn "movsi__update" + [(set (mem:SI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))) (match_operand:SI 3 "gpc_reg_operand" "r,r")) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode) + || !gpc_reg_operand (operands[2], Pmode) || (REG_P (operands[0]) && REGNO (operands[0]) == STACK_POINTER_REGNUM))" "@ @@ -9187,7 +9188,7 @@ (match_operand:SI 3 "gpc_reg_operand" "r,r")) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "" + "TARGET_32BIT" "@ stwux %3,%0,%2 stwu %3,%2(%0)" @@ -9197,12 +9198,12 @@ (define_insn "*movhi_update1" [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") - (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I")))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) + && (!avoiding_indexed_address_p (HImode) || !gpc_reg_operand (operands[2], SImode))" "@ lhzux %3,%0,%2 @@ -9212,15 +9213,15 @@ (set_attr "indexed" "yes,no")]) (define_insn "*movhi_update2" - [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") - (zero_extend:SI - (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + [(set (match_operand:EXTHI 3 "gpc_reg_operand" "=r,r") + (zero_extend:EXTHI + (mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (HImode) + || !gpc_reg_operand (operands[2], Pmode))" "@ lhzux %3,%0,%2 lhzu %3,%2(%0)" @@ -9229,15 +9230,15 @@ (set_attr "indexed" "yes,no")]) (define_insn "*movhi_update3" - [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") - (sign_extend:SI - (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + [(set (match_operand:EXTHI 3 "gpc_reg_operand" "=r,r") + (sign_extend:EXTHI + (mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE - && !(avoiding_indexed_address_p (SImode) - && gpc_reg_operand (operands[2], SImode))" + && !(avoiding_indexed_address_p (HImode) + && gpc_reg_operand (operands[2], Pmode))" "@ lhaux %3,%0,%2 lhau %3,%2(%0)" @@ -9247,14 +9248,14 @@ (set_attr "indexed" "yes,no")]) (define_insn "*movhi_update4" - [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))) + [(set (mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))) (match_operand:HI 3 "gpc_reg_operand" "r,r")) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (HImode) + || !gpc_reg_operand (operands[2], Pmode))" "@ sthux %3,%0,%2 sthu %3,%2(%0)" @@ -9264,13 +9265,13 @@ (define_insn "*movqi_update1" [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") - (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (mem:QI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I")))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (QImode) + || !gpc_reg_operand (operands[2], Pmode))" "@ lbzux %3,%0,%2 lbzu %3,%2(%0)" @@ -9279,15 +9280,15 @@ (set_attr "indexed" "yes,no")]) (define_insn "*movqi_update2" - [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") - (zero_extend:SI - (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + [(set (match_operand:EXTQI 3 "gpc_reg_operand" "=r,r") + (zero_extend:EXTQI + (mem:QI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (QImode) + || !gpc_reg_operand (operands[2], Pmode))" "@ lbzux %3,%0,%2 lbzu %3,%2(%0)" @@ -9296,14 +9297,14 @@ (set_attr "indexed" "yes,no")]) (define_insn "*movqi_update3" - [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))) + [(set (mem:QI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))) (match_operand:QI 3 "gpc_reg_operand" "r,r")) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (QImode) + || !gpc_reg_operand (operands[2], Pmode))" "@ stbux %3,%0,%2 stbu %3,%2(%0)" @@ -9311,47 +9312,49 @@ (set_attr "update" "yes") (set_attr "indexed" "yes,no")]) -(define_insn "*movsf_update1" - [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") - (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] +(define_insn "*mov_update1" + [(set (match_operand:SFDF 3 "gpc_reg_operand" "=,") + (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I")))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_HARD_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (mode) + || !gpc_reg_operand (operands[2], Pmode))" "@ - lfsux %3,%0,%2 - lfsu %3,%2(%0)" + lfux %3,%0,%2 + lfu %3,%2(%0)" [(set_attr "type" "fpload") (set_attr "update" "yes") - (set_attr "indexed" "yes,no")]) + (set_attr "indexed" "yes,no") + (set_attr "size" "")]) -(define_insn "*movsf_update2" - [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:SF 3 "gpc_reg_operand" "f,f")) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] +(define_insn "*mov_update2" + [(set (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))) + (match_operand:SFDF 3 "gpc_reg_operand" ",")) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_HARD_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (mode) + || !gpc_reg_operand (operands[2], Pmode))" "@ - stfsux %3,%0,%2 - stfsu %3,%2(%0)" + stfux %3,%0,%2 + stfu %3,%2(%0)" [(set_attr "type" "fpstore") (set_attr "update" "yes") - (set_attr "indexed" "yes,no")]) + (set_attr "indexed" "yes,no") + (set_attr "size" "")]) (define_insn "*movsf_update3" [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") - (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (mem:SF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I")))) + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_SOFT_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (SFmode) + || !gpc_reg_operand (operands[2], Pmode))" "@ lwzux %3,%0,%2 lwzu %3,%2(%0)" @@ -9360,14 +9363,14 @@ (set_attr "indexed" "yes,no")]) (define_insn "*movsf_update4" - [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))) + [(set (mem:SF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") + (match_operand:P 2 "reg_or_short_operand" "r,I"))) (match_operand:SF 3 "gpc_reg_operand" "r,r")) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:P 0 "gpc_reg_operand" "=b,b") + (plus:P (match_dup 1) (match_dup 2)))] "TARGET_SOFT_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" + && (!avoiding_indexed_address_p (SFmode) + || !gpc_reg_operand (operands[2], Pmode))" "@ stwux %3,%0,%2 stwu %3,%2(%0)" @@ -9375,39 +9378,6 @@ (set_attr "update" "yes") (set_attr "indexed" "yes,no")]) -(define_insn "*movdf_update1" - [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d") - (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_HARD_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" - "@ - lfdux %3,%0,%2 - lfdu %3,%2(%0)" - [(set_attr "type" "fpload") - (set_attr "update" "yes") - (set_attr "indexed" "yes,no") - (set_attr "size" "64")]) - -(define_insn "*movdf_update2" - [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:DF 3 "gpc_reg_operand" "d,d")) - (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") - (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_HARD_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (SImode) - || !gpc_reg_operand (operands[2], SImode))" - "@ - stfdux %3,%0,%2 - stfdu %3,%2(%0)" - [(set_attr "type" "fpstore") - (set_attr "update" "yes") - (set_attr "indexed" "yes,no")]) - ;; After inserting conditional returns we can sometimes have ;; unnecessary register moves. Unfortunately we cannot have a @@ -9771,14 +9741,14 @@ emit_stack_clash_protection_probe_loop_start (&loop_lab, &end_loop, last_addr, rotated); - if (Pmode == SImode) + if (TARGET_32BIT) emit_insn (gen_movsi_update_stack (stack_pointer_rtx, stack_pointer_rtx, update, chain)); else - emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx, - stack_pointer_rtx, - update, chain)); + emit_insn (gen_movdi_update_stack (stack_pointer_rtx, + stack_pointer_rtx, + update, chain)); emit_stack_clash_protection_probe_loop_end (loop_lab, end_loop, last_addr, rotated); } @@ -9802,7 +9772,7 @@ neg_op0 = GEN_INT (-INTVAL (operands[1])); insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack - : gen_movdi_di_update_stack)) + : gen_movdi_update_stack)) (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); /* Since we didn't use gen_frame_mem to generate the MEM, grab