From: Nicolai Hähnle Date: Mon, 15 May 2017 22:19:01 +0000 (+0200) Subject: ac,radeonsi: move some VS input descriptions to ac_shader_abi X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61ad2f13c3c9e3a832b6d16c9302dc846c6eea43;p=mesa.git ac,radeonsi: move some VS input descriptions to ac_shader_abi v2: use LLVM values instead of function parameter indices Reviewed-by: Marek Olšák --- diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h new file mode 100644 index 00000000000..e10550b8eb2 --- /dev/null +++ b/src/amd/common/ac_shader_abi.h @@ -0,0 +1,40 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef AC_SHADER_ABI_H +#define AC_SHADER_ABI_H + +#include + +/* Document the shader ABI during compilation. This is what allows radeonsi and + * radv to share a compiler backend. + */ +struct ac_shader_abi { + LLVMValueRef base_vertex; + LLVMValueRef start_instance; + LLVMValueRef draw_id; + LLVMValueRef vertex_id; + LLVMValueRef instance_id; +}; + +#endif /* AC_SHADER_ABI_H */ diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 5da8f65135c..26ed697319f 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -67,6 +67,7 @@ struct si_shader_output_values */ struct si_function_info { LLVMTypeRef types[100]; + LLVMValueRef *assign[100]; unsigned num_sgpr_params; unsigned num_params; }; @@ -125,8 +126,9 @@ static void si_init_function_info(struct si_function_info *fninfo) fninfo->num_sgpr_params = 0; } -static unsigned add_arg(struct si_function_info *fninfo, - enum si_arg_regfile regfile, LLVMTypeRef type) +static unsigned add_arg_assign(struct si_function_info *fninfo, + enum si_arg_regfile regfile, LLVMTypeRef type, + LLVMValueRef *assign) { assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params); @@ -137,9 +139,16 @@ static unsigned add_arg(struct si_function_info *fninfo, fninfo->num_sgpr_params = fninfo->num_params; fninfo->types[idx] = type; + fninfo->assign[idx] = assign; return idx; } +static unsigned add_arg(struct si_function_info *fninfo, + enum si_arg_regfile regfile, LLVMTypeRef type) +{ + return add_arg_assign(fninfo, regfile, type, NULL); +} + static void add_arg_checked(struct si_function_info *fninfo, enum si_arg_regfile regfile, LLVMTypeRef type, unsigned idx) @@ -374,8 +383,7 @@ static LLVMValueRef get_instance_index_for_fetch( { struct gallivm_state *gallivm = &ctx->gallivm; - LLVMValueRef result = LLVMGetParam(ctx->main_fn, - ctx->param_instance_id); + LLVMValueRef result = ctx->abi.instance_id; /* The division must be done before START_INSTANCE is added. */ if (divisor != ctx->i32_1) @@ -1472,16 +1480,13 @@ static void declare_system_value(struct si_shader_context *ctx, switch (decl->Semantic.Name) { case TGSI_SEMANTIC_INSTANCEID: - value = LLVMGetParam(ctx->main_fn, - ctx->param_instance_id); + value = ctx->abi.instance_id; break; case TGSI_SEMANTIC_VERTEXID: value = LLVMBuildAdd(gallivm->builder, - LLVMGetParam(ctx->main_fn, - ctx->param_vertex_id), - LLVMGetParam(ctx->main_fn, - ctx->param_base_vertex), ""); + ctx->abi.vertex_id, + ctx->abi.base_vertex, ""); break; case TGSI_SEMANTIC_VERTEXID_NOBASE: @@ -1503,17 +1508,16 @@ static void declare_system_value(struct si_shader_context *ctx, indexed = LLVMBuildTrunc(gallivm->builder, indexed, ctx->i1, ""); value = LLVMBuildSelect(gallivm->builder, indexed, - LLVMGetParam(ctx->main_fn, ctx->param_base_vertex), - ctx->i32_0, ""); + ctx->abi.base_vertex, ctx->i32_0, ""); break; } case TGSI_SEMANTIC_BASEINSTANCE: - value = LLVMGetParam(ctx->main_fn, ctx->param_start_instance); + value = ctx->abi.start_instance; break; case TGSI_SEMANTIC_DRAWID: - value = LLVMGetParam(ctx->main_fn, ctx->param_draw_id); + value = ctx->abi.draw_id; break; case TGSI_SEMANTIC_INVOCATIONID: @@ -4035,6 +4039,11 @@ static void si_create_function(struct si_shader_context *ctx, lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG); } + for (i = 0; i < fninfo->num_params; ++i) { + if (fninfo->assign[i]) + *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i); + } + if (max_workgroup_size) { si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size", max_workgroup_size); @@ -4182,9 +4191,9 @@ static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx, { ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS)); - ctx->param_base_vertex = add_arg(fninfo, ARG_SGPR, ctx->i32); - ctx->param_start_instance = add_arg(fninfo, ARG_SGPR, ctx->i32); - ctx->param_draw_id = add_arg(fninfo, ARG_SGPR, ctx->i32); + add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex); + add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance); + add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id); ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32); } @@ -4194,12 +4203,12 @@ static void declare_vs_input_vgprs(struct si_shader_context *ctx, { struct si_shader *shader = ctx->shader; - ctx->param_vertex_id = add_arg(fninfo, ARG_VGPR, ctx->i32); + add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id); if (shader->key.as_ls) { ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32); - ctx->param_instance_id = add_arg(fninfo, ARG_VGPR, ctx->i32); + add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id); } else { - ctx->param_instance_id = add_arg(fninfo, ARG_VGPR, ctx->i32); + add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id); ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32); } add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */ @@ -5232,8 +5241,7 @@ si_generate_gs_copy_shader(struct si_screen *sscreen, preload_ring_buffers(&ctx); LLVMValueRef voffset = - lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn, - ctx.param_vertex_id), 4); + lp_build_mul_imm(uint, ctx.abi.vertex_id, 4); /* Fetch the vertex stream ID.*/ LLVMValueRef stream_id; @@ -6637,9 +6645,6 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx, num_input_vgprs; unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0; - ctx->param_vertex_id = first_vs_vgpr; - ctx->param_instance_id = first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1); - si_init_function_info(&fninfo); /* 4 preloaded VGPRs + vertex load indices as prolog outputs */ @@ -6659,6 +6664,9 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx, returns[num_returns++] = ctx->f32; } + fninfo.assign[first_vs_vgpr] = &ctx->abi.vertex_id; + fninfo.assign[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)] = &ctx->abi.instance_id; + /* Vertex load indices. */ for (i = 0; i <= key->vs_prolog.last_input; i++) returns[num_returns++] = ctx->f32; @@ -6721,7 +6729,7 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx, } else { /* VertexID + BaseVertex */ index = LLVMBuildAdd(gallivm->builder, - LLVMGetParam(func, ctx->param_vertex_id), + ctx->abi.vertex_id, LLVMGetParam(func, user_sgpr_base + SI_SGPR_BASE_VERTEX), ""); } diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index 6b98bca2708..9b5e0b4e535 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -29,6 +29,7 @@ #include "gallivm/lp_bld_init.h" #include "gallivm/lp_bld_tgsi.h" #include "tgsi/tgsi_parse.h" +#include "ac_shader_abi.h" #include "ac_llvm_util.h" #include "ac_llvm_build.h" @@ -67,6 +68,8 @@ struct si_shader_context { /* Whether the prolog will be compiled separately. */ bool separate_prolog; + struct ac_shader_abi abi; + /** This function is responsible for initilizing the inputs array and will be * called once for each input declared in the TGSI shader. */ @@ -125,13 +128,8 @@ struct si_shader_context { int param_merged_scratch_offset; /* API VS */ int param_vertex_buffers; - int param_base_vertex; - int param_start_instance; - int param_draw_id; - int param_vertex_id; int param_rel_auto_id; int param_vs_prim_id; - int param_instance_id; int param_vertex_index0; /* VS states and layout of LS outputs / TCS inputs at the end * [0] = clamp vertex color